메뉴 건너뛰기




Volumn 8, Issue 4-5, 2006, Pages 411-430

Putting it all together - Formal verification of the VAMP

Author keywords

Cache memory interface; Complete microprocessor verification; Floating point unit; Formal methods; Model checking; Theorem proving; Tomasulo scheduler

Indexed keywords


EID: 33748997918     PISSN: 14332779     EISSN: 14332787     Source Type: Journal    
DOI: 10.1007/s10009-006-0204-6     Document Type: Conference Paper
Times cited : (48)

References (49)
  • 1
    • 33749019268 scopus 로고    scopus 로고
    • The VAMP project. Website
    • The VAMP project. Website: http://www-wjp.cs.uni-sb.de/projects/ verification
  • 2
    • 33749029570 scopus 로고    scopus 로고
    • Formal verification of an IEEE floating point adder
    • Master's Thesis, Saarland University, Germany
    • Berg, C.: Formal verification of an IEEE floating point adder. Master's Thesis, Saarland University, Germany (2001)
    • (2001)
    • Berg, C.1
  • 3
    • 84947223950 scopus 로고    scopus 로고
    • Formal verification of the VAMP floating point unit
    • vol. 2144 of LNCS, Springer, Heidelberg
    • Berg, C., Jacobi, C.: Formal verification of the VAMP floating point unit. In: Proceedings of the 11th CHARME, vol. 2144 of LNCS, pp. 325-339. Springer, Heidelberg (2001)
    • (2001) Proceedings of the 11th CHARME , pp. 325-339
    • Berg, C.1    Jacobi, C.2
  • 6
    • 33646424926 scopus 로고    scopus 로고
    • Putting it all together - Formal verification of the VAMP
    • PhD Thesis, Saarland University, Germany
    • Beyer, S.: Putting it all together - Formal verification of the VAMP. PhD Thesis, Saarland University, Germany (2005)
    • (2005)
    • Beyer, S.1
  • 7
    • 24644515293 scopus 로고    scopus 로고
    • Correct hardware by synthesis from PVS
    • Internal Report, available at
    • Beyer, S., Jacobi, C., Kröning, D., Leinenbach, D.: Correct hardware by synthesis from PVS. Internal Report, available at http://www-wjp.cs.uni-sb.de/publikationen/BJKL02.pdf (2002)
    • (2002)
    • Beyer, S.1    Jacobi, C.2    Kröning, D.3    Leinenbach, D.4
  • 8
    • 0142245459 scopus 로고    scopus 로고
    • Instantiating uninterpreted functional units and memory system: Functional verification of the VAMP
    • In: Geist, D., Tronci, E. (eds.) vol. 2860 of LNCS, Springer, Heidelberg
    • Beyer, S., Jacobi, C., Kröning, D., Leinenbach, D., Paul, W.: Instantiating uninterpreted functional units and memory system: Functional verification of the VAMP. In: Geist, D., Tronci, E. (eds.) CHARME 2003, vol. 2860 of LNCS, pp. 51-65. Springer, Heidelberg (2003)
    • (2003) CHARME 2003 , pp. 51-65
    • Beyer, S.1    Jacobi, C.2    Kröning, D.3    Leinenbach, D.4    Paul, W.5
  • 9
    • 0141667730 scopus 로고
    • The FM9001 microprocessor proof
    • Technical Report Technical Report 86, Computational Logic Inc
    • Brock, B., Hunt, W.A., Kaufmann, M.: The FM9001 microprocessor proof. Technical Report Technical Report 86, Computational Logic Inc. (1994)
    • (1994)
    • Brock, B.1    Hunt, W.A.2    Kaufmann, M.3
  • 10
    • 0031190775 scopus 로고    scopus 로고
    • The DUAL-EVAL hardware description language and its use in the formal specification and verification of the FM9001 microprocessor
    • Brock, B.C., Hunt, W.A.: The DUAL-EVAL hardware description language and its use in the formal specification and verification of the FM9001 microprocessor. Form. Methods Syst. Des. 11, 71-107 (1997)
    • (1997) Form. Methods Syst. Des. , vol.11 , pp. 71-107
    • Brock, B.C.1    Hunt, W.A.2
  • 11
    • 84958772916 scopus 로고
    • Automatic verification of pipelined microprocessors control
    • Springer-Verlag, Standford, CA
    • Burch, J.R., Dill, D.L.: Automatic verification of pipelined microprocessors control. In: CAV 94, vol. 818, pp. 68-80. Springer-Verlag, Standford, CA (1994)
    • (1994) CAV 94 , vol.818 , pp. 68-80
    • Burch, J.R.1    Dill, D.L.2
  • 12
    • 33748528358 scopus 로고    scopus 로고
    • A bitvectors library for PVS
    • Technical Report 110274, NASA Langley Research Center
    • Butler, R.W., Miner, P.S., Srivas, M.K., Greve, D.A., Miller, S.P.: A bitvectors library for PVS. Technical Report 110274, NASA Langley Research Center (1996)
    • (1996)
    • Butler, R.W.1    Miner, P.S.2    Srivas, M.K.3    Greve, D.A.4    Miller, S.P.5
  • 13
    • 84957677881 scopus 로고    scopus 로고
    • Verification of all circuits in a floating-point unit using word-level model checking
    • In: vol. 1166 of LNCS, Springer, Heidelberg
    • Chen, Y.-A., Clarke, E.M., Ho, P.-H., Hoskote, Y., Kam, T., Khaira, M., O'Leary, J.W., Zhao, X.: Verification of all circuits in a floating-point unit using word-level model checking. In: FMCAD, vol. 1166 of LNCS, pp. 19-33. Springer, Heidelberg (1996)
    • (1996) FMCAD , pp. 19-33
    • Chen, Y.-A.1    Clarke, E.M.2    Ho, P.-H.3    Hoskote, Y.4    Kam, T.5    Khaira, M.6    O'Leary, J.W.7    Zhao, X.8
  • 14
    • 0000938587 scopus 로고    scopus 로고
    • Verifying out-of-order executions
    • In: Chapman & Hall, Montreal, Canada
    • Damm, W., Pnueli, A.: Verifying out-of-order executions. In: Charme IFIP WG10.5, pp. 23-47. Chapman & Hall, Montreal, Canada (1997)
    • (1997) Charme IFIP WG10.5 , pp. 23-47
    • Damm, W.1    Pnueli, A.2
  • 15
    • 84948988996 scopus 로고    scopus 로고
    • The formal design of 1M-gate ASICs
    • In: (eds.) vol. 1522 of LNCS, Gopalakrishnan, G., Windley, P. Springer, Heidelberg
    • Eiriksson, A.P.: The formal design of 1M-gate ASICs. In: Gopalakrishnan, G., Windley, P. (eds.) FMCAD 98, vol. 1522 of LNCS, pp. 49-63. Springer, Heidelberg (1998)
    • (1998) FMCAD 98 , pp. 49-63
    • Eiriksson, A.P.1
  • 16
    • 84949208566 scopus 로고
    • Characterizing correctness properties of parallel programs using fixpoints
    • In: vol. 85 of LNCS, Springer, Heidelberg
    • Emerson, E.A., Clarke, E.M.: Characterizing correctness properties of parallel programs using fixpoints. In: Automata, Languages and Programming, vol. 85 of LNCS. Springer, Heidelberg (1980)
    • (1980) Automata, Languages and Programming
    • Emerson, E.A.1    Clarke, E.M.2
  • 18
    • 33646426020 scopus 로고    scopus 로고
    • Address spaces and virtual memory: Specification, implementation, and correctnesss
    • PhD Thesis, Saarland University, Germany
    • Hillebrand, M.: Address spaces and virtual memory: Specification, implementation, and correctnesss. PhD Thesis, Saarland University, Germany (2005)
    • (2005)
    • Hillebrand, M.1
  • 19
    • 84957082109 scopus 로고    scopus 로고
    • Proof of correctness of a processor with reorder buffer using the completion functions approach
    • In: Springer-Verlag, Trento, Italy
    • Hosabettu, R., Srivas, M., Gopalakrishnan, G.: Proof of correctness of a processor with reorder buffer using the completion functions approach. In: Computer-Aided Verification, CAV '99, vol. 1633, pp. 47-59. Springer-Verlag, Trento, Italy (1999)
    • (1999) Computer-Aided Verification, CAV '99 , vol.1633 , pp. 47-59
    • Hosabettu, R.1    Srivas, M.2    Gopalakrishnan, G.3
  • 20
    • 0032630203 scopus 로고    scopus 로고
    • Verifying the FM9801 microarchitecture
    • Hunt, W.A., Sawada, J.: Verifying the FM9801 microarchitecture. IEEE Micro, pp. 47-55 (1999)
    • (1999) IEEE Micro , pp. 47-55
    • Hunt, W.A.1    Sawada, J.2
  • 21
    • 33748988086 scopus 로고
    • Institute of Electrical and Electronics Engineers. ANSI/IEEE standard 754-1985, IEEE Standard for Binary Floating-Point Arithmetic
    • Institute of Electrical and Electronics Engineers. ANSI/IEEE standard 754-1985, IEEE Standard for Binary Floating-Point Arithmetic (1985)
    • (1985)
  • 22
    • 33749017235 scopus 로고    scopus 로고
    • A formally verified theory of IEEE rounding
    • Unpublished, available at
    • Jacobi, C.: A formally verified theory of IEEE rounding. Unpublished, available at http://www-wjp.cs.uni-sb.de/~cj/ieee-lib.ps (2001)
    • (2001)
    • Jacobi, C.1
  • 23
    • 84937561625 scopus 로고    scopus 로고
    • Formal verification of complex out-of-order pipelines by combining model-checking and theorem-proving
    • In: vol. 2404 of LNCS, Springer, Heidelberg
    • Jacobi, C.: Formal verification of complex out-of-order pipelines by combining model-checking and theorem-proving. In: CAV, vol. 2404 of LNCS. Springer, Heidelberg (2002)
    • (2002) CAV
    • Jacobi, C.1
  • 24
    • 24644487707 scopus 로고    scopus 로고
    • Formal verificaton of a fully IEEE compliant floating point unit
    • PhD Thesis, Saarland University, Germany
    • Jacobi, C.: Formal verificaton of a fully IEEE compliant floating point unit. PhD Thesis, Saarland University, Germany (2002)
    • (2002)
    • Jacobi, C.1
  • 25
    • 24644494700 scopus 로고    scopus 로고
    • Formal verification of the VAMP floating point unit
    • In: Springer (May)
    • Jacobi, C., Berg, C.: Formal verification of the VAMP floating point unit. In: Formal Methods in System Design, pp. 227-266. Springer (May 2005)
    • (2005) Formal Methods in System Design , pp. 227-266
    • Jacobi, C.1    Berg, C.2
  • 26
    • 33646898170 scopus 로고    scopus 로고
    • Automatic formal verification of fused-multiply-add FPUs
    • In IEEE Computer Society
    • Jacobi, C., Weber, K., Paruthi, V., Baumgartner, J.: Automatic formal verification of fused-multiply-add FPUs. In DATE, pp. 1298-1303. IEEE Computer Society (2005)
    • (2005) DATE , pp. 1298-1303
    • Jacobi, C.1    Weber, K.2    Paruthi, V.3    Baumgartner, J.4
  • 27
    • 0001464763 scopus 로고
    • Multiplication of multidigit numbers on automata
    • Karatsuba, A., Ofman, Y.: Multiplication of multidigit numbers on automata. Sov. Phys. Dokl. 7 (1963)
    • (1963) Sov. Phys. Dokl. , vol.7
    • Karatsuba, A.1    Ofman, Y.2
  • 28
    • 24644467181 scopus 로고    scopus 로고
    • Formal verification of pipelined microprocessors
    • PhD Thesis, Saarland University, Germany
    • Kröning, D.: Formal verification of pipelined microprocessors. PhD Thesis, Saarland University, Germany (2001)
    • (2001)
    • Kröning, D.1
  • 30
    • 33748996406 scopus 로고    scopus 로고
    • Proving the correctness of processors with delayed branch using delayed PCs
    • Kröning, D., Müller, S., Paul, W.: Proving the correctness of processors with delayed branch using delayed PCs. Numbers, Information and Complexity, pp. 579-588 (2000)
    • (2000) Numbers, Information and Complexity , pp. 579-588
    • Kröning, D.1    Müller, S.2    Paul, W.3
  • 32
    • 33749031194 scopus 로고    scopus 로고
    • Implementierung eines maschinell verifizierten Prozessors
    • Master's Thesis, Saarland University, Germany
    • Leinenbach, D.: Implementierung eines maschinell verifizierten Prozessors. Master's Thesis, Saarland University, Germany (2002)
    • (2002)
    • Leinenbach, D.1
  • 33
    • 84863924303 scopus 로고    scopus 로고
    • Verification of an implementation of Tomasulo's algorithm by compositional model checking
    • In: Springer, Heidelberg
    • McMillan, K.: Verification of an implementation of Tomasulo's algorithm by compositional model checking. In: CAV 98, vol. 1427. Springer, Heidelberg (1998)
    • (1998) CAV 98 , vol.1427
    • McMillan, K.1
  • 34
    • 84947280188 scopus 로고    scopus 로고
    • Parameterized verification of the FLASH cache coherence protocol by compositional model checking
    • In: vol. 2144 of LNCS, Springer, Heidelberg
    • McMillan, K.: Parameterized verification of the FLASH cache coherence protocol by compositional model checking. In: CHARME 2001, vol. 2144 of LNCS. Springer, Heidelberg (2001)
    • (2001) CHARME 2001
    • McMillan, K.1
  • 35
    • 33749018726 scopus 로고    scopus 로고
    • Entwicklung einer Laufzeitumgebung für den VAMP-Prozessor
    • Master's Thesis, Saarland University, Germany
    • Meyer, C.: Entwicklung einer Laufzeitumgebung für den VAMP-Prozessor. Master's Thesis, Saarland University, Germany (2002)
    • (2002)
    • Meyer, C.1
  • 36
    • 0003725541 scopus 로고
    • Defining the IEEE-854 floating-point standard in PVS
    • Technical Report TM-110167, NASA Langley Research Center
    • Miner, P.S.: Defining the IEEE-854 floating-point standard in PVS. Technical Report TM-110167, NASA Langley Research Center (1995)
    • (1995)
    • Miner, P.S.1
  • 39
    • 84944677742 scopus 로고
    • PVS: A prototype verification system
    • In: vol. 607 of LNAI, Springer, Heidelberg
    • Owre, S., Shankar, N., Rushby, J.M.: PVS: A prototype verification system. In: CADE 11, vol. 607 of LNAI, pp. 748-752. Springer, Heidelberg (1992)
    • (1992) CADE 11 , pp. 748-752
    • Owre, S.1    Shankar, N.2    Rushby, J.M.3
  • 40
    • 0001582662 scopus 로고    scopus 로고
    • A mechanically checked proof of IEEE compliance of the floating point multiplication, division and square root algorithms of the AMD-K7 processor
    • Russinoff, D.M.: A mechanically checked proof of IEEE compliance of the floating point multiplication, division and square root algorithms of the AMD-K7 processor. LMS J. Comput. Math. 1, 148-200 (1998)
    • (1998) LMS J. Comput. Math. , vol.1 , pp. 148-200
    • Russinoff, D.M.1
  • 41
    • 24644496622 scopus 로고    scopus 로고
    • A case study in formal verification of register-transfer logic with ACL2: The floating point adder of the AMD Athlon processor
    • In: vol. 1954 of LNCS, Springer, Heidelberg
    • Russinoff, D.M.: A case study in formal verification of register-transfer logic with ACL2: The floating point adder of the AMD Athlon processor. In: FMCAD-00, vol. 1954 of LNCS. Springer, Heidelberg (2000)
    • (2000) FMCAD-00
    • Russinoff, D.M.1
  • 42
    • 84947428590 scopus 로고    scopus 로고
    • Trace table based approach for pipelined microprocessor verification
    • In: vol. 1254 of LNCS, Springer, Heidelberg
    • Sawada, J., Hunt, W.A.: Trace table based approach for pipelined microprocessor verification. In: CAV 97, vol. 1254 of LNCS. Springer, Heidelberg (1997)
    • (1997) CAV 97
    • Sawada, J.1    Hunt, W.A.2
  • 43
    • 84863974979 scopus 로고    scopus 로고
    • Processor verification with precise exceptions and speculative execution
    • In: vol. 1427 of LNCS, Springer, Heidelberg
    • Sawada, J., Hunt, W.A.: Processor verification with precise exceptions and speculative execution. In: CAV 98, vol. 1427 of LNCS. Springer, Heidelberg (1998)
    • (1998) CAV 98
    • Sawada, J.1    Hunt, W.A.2
  • 44
    • 0036500716 scopus 로고    scopus 로고
    • Verification of the FM9801 microprocessor: An out-of-order microprocessor model with speculative execution, exceptions, and self-modifying code
    • Sawada, J., Hunt, W.A.: Verification of the FM9801 microprocessor: An out-of-order microprocessor model with speculative execution, exceptions, and self-modifying code. Form. Methods Syst. Des. 20 (2), 187-222 (2002)
    • (2002) Form. Methods Syst. Des. , vol.20 , Issue.2 , pp. 187-222
    • Sawada, J.1    Hunt, W.A.2
  • 45
    • 0032645151 scopus 로고    scopus 로고
    • CACHET: An adaptive cache coherence protocol for distributed shared-memory systems
    • Shen, X., Arvind, Rudolph, L.: CACHET: An adaptive cache coherence protocol for distributed shared-memory systems. In: International Conference on Supercomputing (1999)
    • (1999) International Conference on Supercomputing
    • Shen, X.1    Arvind2    Rudolph, L.3
  • 47
    • 84881120330 scopus 로고    scopus 로고
    • Proofs of correctness of cache-coherence protocols
    • In: vol. 2021 of LNCS, Springer, Heidelberg
    • Stoy, J., Shen, X., Arvind: Proofs of correctness of cache-coherence protocols. In: FME, vol. 2021 of LNCS. Springer, Heidelberg (2001)
    • (2001) FME
    • Stoy, J.1    Shen, X.2    Arvind3
  • 48
    • 84861449103 scopus 로고    scopus 로고
    • Superscalar processor verification using efficient reductions of the logic of equality with uninterpreted functions to propositional logic
    • In: vol. 1703 of LNCS Springer, Heidelberg
    • Velev, M.N., Bryant, R.E.: Superscalar processor verification using efficient reductions of the logic of equality with uninterpreted functions to propositional logic. In: CHARME, vol. 1703 of LNCS. Springer, Heidelberg (1999)
    • (1999) CHARME
    • Velev, M.N.1    Bryant, R.E.2
  • 49
    • 0033684177 scopus 로고    scopus 로고
    • Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction
    • In: DAC. ACM
    • Velev, M.N., Bryant, R.E.: Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction. In: DAC. ACM (2000)
    • (2000)
    • Velev, M.N.1    Bryant, R.E.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.