Automatic formal verification of fused-multiply-add FPUs

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn II, Issue , 2005, Pages 1298-1303

  Jacobi, Christian ^a   Weber, Kai ^a   Paruthi, Viresh ^b   Baumgartner, Jason ^b  

^a IBM   (Germany)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC MODEL REDUCTION; CASE-SPLITTING; FLOATING POINT UNITS (FPU); MULTIPLIER ISOLATION;

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; MATHEMATICAL MODELS; PIPELINE PROCESSING SYSTEMS;

PROGRAM PROCESSORS;

EID: 33646898170     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.75     Document Type: Conference Paper

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