Trace table based approach for pipelined microprocessor verification

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1254, Issue , 1997, Pages 364-375

  Sawada, Jun ^a   Hunt, Warren A ^b  

^a University of Texas at Austin   (United States)

^b Computational Logic Inc ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED ANALYSIS; INTEGRATED CIRCUIT DESIGN; MACHINE DESIGN;

DYNAMIC RESOLUTION; EXECUTED INSTRUCTIONS; INVARIANT PROPERTIES; MICROPROCESSOR DESIGNS; MICROPROCESSOR VERIFICATION; OUT-OF-ORDER COMPLETION; OUT-OF-ORDER EXECUTION; PIPELINED IMPLEMENTATION;

PIPELINES;

EID: 84947428590     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-63166-6_36     Document Type: Conference Paper

References (14)

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