Verifying the FM9801 microarchitecture

IEEE Micro

Volumn 19, Issue 3, 1999, Pages 47-55

  Hunt Jr , Warren A ^a,b   Sawada, Jun ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER DEBUGGING; COMPUTER SIMULATION; FORMAL LOGIC; PIPELINE PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS); SYSTEMS ANALYSIS; THEOREM PROVING;

INSTRUCTION SET ARCHITECTURAL; MICROARCHITECTURE; REGISTER TRANSFER LEVEL;

MICROPROCESSOR CHIPS;

EID: 0032630203     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.768503     Document Type: Article

References (14)

1. M. Kaufmann and J.S. Moore, "ACL2: An Industrial Strength Version of Nqthm," Proc. 11th Ann. Conf. Computer Assurance, COMPASS-96, IEEE Computer Soc. Press, Los Alamitos, Calif., June 1996, pp. 23-34.
2. B.C. Brock and W.A. Hunt, Jr., "The DUAL-EVAL Hardware Description Language and Its Use in the Formal Specification and Verification of the FM9001 Microprocessor," Formal Methods in System Design, Kluwer Academic Publishers, Dordrecht, Netherlands, Vol. 11, Issue 1, July, 1997, pp. 71-104.
3. M.K. Srivas and S.P. Miller, Formal Verification of an Avionics Microprocessor, Tech. Report CSL-95-04, SRI Int'l Computer Science Laboratory, Menlo Park, Calif., June 1995.
4. B.C. Brock, M. Kaufmann, and J.S. Moore, "ACL2 Theorems About Commercial Microprocessors," Formal Methods in Computer-Aided Design (FMCAD'96), Lecture Notes in Computer Science 1166, M. Srivas and A. Camilleri, eds., Springer Verlag, Berlin, 1996, pp. 275-293; also at http://www.es.utexas. edu/users/moore/acl2/index.html.
5. K.L. McMillan, Symbolic Model Checking, Kluwer, Boston/Dordrecht/London, 1993.
6. Formal Semantics for VHDL, C.D. Koos and P.T. Breuer, eds., Kluwer, 1995.
7. M.J.C. Gordon, "The Semantic Challenge of Verilog HDL," Proc. 10th Ann. IEEE Symp. Logic in Computer Sci., (LICS'95), IEEE CS Press, pp. 136-145.
8. B.C. Brock, W.A. Hunt, Jr., and M. Kaufmann, The FM9001 Microprocessor Proof, Tech. Report 86, Computational Logic, Inc., Austin, Tex., Dec. 1994, http://www.cli.com/reports/files/86.ps.
9. J.R. Burch and D.L. Dill, "Automatic Verification of Pipelined Microprocessor Control," Proc. Computer-Aided Verification (CAV '94), Lecture Notes in Computer Sci. 818, D. Dill, ed., June 1994, Springer Verlag, pp. 68-80.
10. J. R. Burch, "Techniques for Verifying Superscalar Microprocessors," Proc. Design Automation Conf. (DAC '96), ACM Press, New York, June 1996, pp. 552-557.
11. J. Sawada and W. Hunt, Jr., "Processor Verification with Precise Exceptions and Speculative Execution," Proc. Computer-Aided Verification (CAV '98), Lecture Notes in Computer Science 1427, A.J. Hu and M.Y. Vardi, eds., Springer Verlag, 1998, pp. 135-146.
12. C-J.H. Seger and R.E. Bryant, Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories, Tech. Report 93-8, Computer Sci. Dept, Univ. of British Columbia, Vancouver, 1993.
13. J. Sawada and W. Hunt, Jr., "Trace Table Based Approach for Pipelined Microprocessor Verification," Proc. Computer-Aided Verification, CAV '97, Lecture Notes in Computer Science 1254, Springer Verlag, 1997, pp. 364-375.
14. K.L. McMillan, "Verification of an Implementation of Tomasulo's Algorithm by Compositional Model Checking," Proc. Computer-Aided Verification (CAV '98), Lecture Notes in Computer Science 1427, A.J. Hu and M.Y. Vardi, eds., Springer Verlag, 1998, pp. 110-121.