Verification of FM9801: An out-of-order microprocessor model with speculative execution, exceptions, and program-modifying capability

Formal Methods in System Design

Volumn 20, Issue 2, 2002, Pages 187-222

  Sawada, Jun ^a   Hunt Jr , Warren A ^a  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

Formal verification; Out of order execution; Pipelined microprocessor; Theorem prover

Indexed keywords

ALGORITHMS; FORMAL LOGIC; MICROPROCESSOR CHIPS; PIPELINE PROCESSING SYSTEMS; REDUCED INSTRUCTION SET COMPUTING; THEOREM PROVING;

FORMAL VERIFICATION; OUT OF ORDER MICROPROCESSOR MODEL; PIPELINED EXECUTION; TOMASULO ALGORITHMS;

DESIGN FOR TESTABILITY;

EID: 0036500716     PISSN: 09259856     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1014122630277     Document Type: Article

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