An approach for implementing efficient superscalar CISC processors

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn 2006, Issue , 2006, Pages 41-52

  Hu, Shiliang ^a   Kim, Ilhyun ^a,b   Lipasti, Mikko H ^a   Smith, James E ^a  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CODES (SYMBOLS); COMPUTATIONAL COMPLEXITY; COMPUTER AIDED LANGUAGE TRANSLATION; COMPUTER HARDWARE; COMPUTER SOFTWARE; REDUCED INSTRUCTION SET COMPUTING; SCHEDULING;

CISC SUPERBLOCKS; DYNAMIC TRANSLATION SOFTWARE; REGISTER FILE PORTS; SUPERSCALAR PROCESSORS;

PROGRAM PROCESSORS;

EID: 33748847120     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2006.1598111     Document Type: Conference Paper

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