Using dynamic binary translation to fuse dependent instructions

International Symposium on Code Generation and Optimization, CGO

Volumn , Issue , 2004, Pages 213-224

  Hu, Shiliang ^a   Smith, James E ^b  

^a University of Wisconsin Madison   (United States)

^b University of Wisconsin Madison   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY TRANSLATION; FUSE DEPENDENT INSTRUCTIONS;

COMPUTER AIDED INSTRUCTION; PIPELINE PROCESSING SYSTEMS; PROGRAM PROCESSORS; SCHEDULING;

PARALLEL PROCESSING SYSTEMS;

EID: 3042606567     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (24)

1. rd Int'l Symp. on Microarchitecture, pp. 57-66, Dec. 2000.
2. th Int'l Symp. on Microarchitecture, pp. 204-213, Dec. 2001.
3. th Int'l Symp. on Microarchitecture, pp. 277-288, Dec. 2003.
4. th Int'l Symp. on Computer Architecture, pp. 71-82, May 2002.
5. th Int'l Symp. of Computer Architecture, pp. 306-315, May 2000.
6. th Int'l Symp. on Computer Architecture, pp. 37-46, May 2002.
7. th Int'l Symp. on Computer Architecture, pp. 28-38, June 2003.
8. th Int'l Conf. on Supercomputing, pp 327-335, June 2000.
9. th Int'l Conf. on Supercomputing, pp. 312-320, June 2001.
10. th Int'l Symp. on High Performance Computer Architecture, pp. 27-36, Jan. 2001.
11. L. Gwennap, "Intel P6 Uses Decoupled Superscalar Design", Micro processor Report, Vol. 9 No. 2, Feb. 1995.
12. Simcha Gochamn et al., "The Intel Pentium M Processor: Microarchitecture and Performance", Intel Technology Journal, vol7, issue 2, 2003.
13. Glenn Hinton et al., "The Microarchitecture of the Pentium 4 Processor", Intel Technology Journal. Q1, 2001.
14. C. N. Keltcher, et al., "The AMD Opteron Processor for Multiprocessor Servers" IEEE MICRO, Mar.-Apr. 2003, pp. 66-76.
15. J. M. Tendler, et al., "POWER 4 System Microarchitecture", IBM Journal of Research and Development, Vol. 46. No. 1, 2002.
16. Unpublished document, "CRAY-2 Central Processor", circa 1979, http://www.ece.wisc.edu/~jes/papers/cray2a.pdf
17. A. Klaiber, "The Technology Behind Crusoe Processors", Transmeta Technical Brief, 2000.
18. K. Ebcioglu et al., "Dynamic Binary Translation and Optimization", IEEE Transactions on Computers, Vol. 50, No. 6, pp. 529-548. June 2001.
19. st Int'l Symp. on Code Generation and Optomization, pp25-35, Mar. 2003.
20. Vasanth Bala, Evelyn Duesterwald, Sanjeev Banerjia, "Dynamo: A Transparent Dynamic Optimization System", Int'l Symp. on Programming Language Design and Implementation, pp. 1-12, Jun. 2000.
21. "BOCHS: The open source IA-32 Emulation Project", http://bochs.sourceforge.net
22. th Int'l Symp. on Architecture Support for Programming Languages and Operating System", pp. 151-158, Oct. 1998.
23. Wen-mei W. Hwu, Scott A. Mahlke, William Y. Chen, "The Superblock: An Effective Technique for VLIW and Superscalar Compilation", The Journal of Supercomputing, 7(1-2) pp. 229-248, 1993.
24. S. Vassiliadis, J. Phillips, and B. Blaner, "Interlock Collapsing ALUs", IEEE Transactions on Computers, July 1993, pp. 825-839.