An architectural framework for runtime optimization

IEEE Transactions on Computers

Volumn 50, Issue 6, 2001, Pages 567-589

  Merten, Matthew C ^a,b   Trick, Andrew R ^a,c   Barnes, Ronald D ^a,b   Nystrom, Erik M ^a,b   George, Christopher N ^a,b   Gyllenhaal, John C ^d   Hwu, Wen Mei W ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^c HEWLETT PACKARD COMPANY   (United States)

^d LAWRENCE LIVERMORE NATIONAL LABORATORY   (United States)

Author keywords

Code layout; Dynamic optimization; Hardware profiling; Low overhead profiling; Partial function inlining; Postlink optimization; Program hot spot; Runtime optimization; Trace formation and optimization

Indexed keywords

RUNTIME OPTIMIZATION;

CODES (SYMBOLS); COMPUTER ARCHITECTURE; COMPUTER HARDWARE; MICROPROCESSOR CHIPS; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS;

PARALLEL PROCESSING SYSTEMS;

EID: 0035365019     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.931894     Document Type: Article

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