Continuous optimization

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2005, Pages 86-97

  Fahs, Brian ^a   Rafacz, Todd ^a   Patel, Sanjay J ^a   Lumetta, Steven S ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; OPTIMIZATION; PROGRAM PROCESSORS;

DATAFLOW OPTIMIZATION; PROCESSOR PIPELINES;

HARDWARE;

EID: 27544446445     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/isca.2005.19     Document Type: Conference Paper

References (28)

1. Y. Almog, R. Rosner, N. Schwartz, and A. Schmorak. Specialized dynamic optimizations for high-performance energy-efficient microarchitecture. In Proceedings of the 2nd International Symposium on Code Generation and Optimization, pages 137-148, 2004.
2. V. Bala, E. Duesterwald, and S. Banerjia. Transparent dynamic optimization: The design and implementation of Dynamo. Technical Report HPL-1999-78, Hewlett-Packard Laboratories, June 1999.
3. R. D. Barnes, E. M. Nystrom, J. W. Sias, S. J. Patel, N. Navarro, and W. mei W. Hwu. Beating in-order stalls with "flea-flicker" two-pass pipelining. In Proceedings of the 36th Annual International Symposium on Microarchitecture, pages 387-398, 2003.
4. M. Bekerman, A. Yoaz, F. Gabbay, S. Jourdan, M. Kalaev, and R. Ronen. Early load address resolution via register tracking. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 306-315, 2000.
5. D. Bruening, T. Garnett, and S. Amarasinghe. An infrastructure for adaptive dynamic optimization. In Proceedings of the 1st International Symposium on Code Generation and Optimization, pages 265-275, 2003.
6. J. A. Butts and G. S. Sohi. Dynamic dead-instruction dectection and elimination. In Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 199-210, 2002.
7. H. Chen, W.-C. Hsu, J. Lu, P.-C. Yew, and D.-Y. Chen. Dynamic trace selection using performance monitoring hardware sampling. In Proceedings of the Ist International Symposium on Code Generation and Optimization, pages 79-90, 2003.
8. W. Chen, S. Lerner, R. Chaiken, and D. Gilles. Mojo: A Dynamic Optimization System. In 3rd Workshop on Feedback-Directed and Dynamic Optimization, 2000.
9. B. Fahs, S. Bose, M. Crum, B. Slechta, F. Spadini, T. Tung, S. J. Patel, and S. S. Lumetta. A performance characterization of a hardware mechanism for dynamic optimization. In Proceedings of the 34th Annual International Symposium on Microarchitecutre, 2001.
10. B. Fahs, T. Rafacz, S. J. Patel, and S. S. Lumetta. Continuous optimization. Technical Report UILU-ENG-04-2207, University of Illinois at Urbana-Champaign, August 2004.
11. D. H. Friendly, S. J. Patel, and Y. N. Patt. Putting the fill unit to work: Dynamic optimizations for trace cache microprocessors. In Proceedings of the 31st Annual International Symposium on Microarchitecture, pages 173-181, 1998.
12. A. Hartstein and T. R. Puzak. Optimum power/performance pipeline depth. In Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, pages 117-128, 2003.
13. G. Hinton, D. Sager, M. Upton, D. Boggs, D. Carmean, A. Kyker, and P. Roussel. The microarchitecture of the Pentium 4 processor. Intel Technology Journal, Q(1), 2001.
14. Q. Jacobson and J. E. Smith. Instruction pre-processing in trace processors. In Proceedings of the 5th International Symposium on High Performance Computer Architecture, 1999.
15. S. Jourdan, R. Ronen, and M. Bekerman. A novel renaming scheme to exploit value temporal locality through physical register reuse and unification. In Proceedings of the 31st Annual International Symposium on Microarchitecture, pages 216-225, 1998.
16. I. Kim and M. H. Lipasti. Implementing optimizations at decode time. In Proceedings of the 29th annual international symposium on Computer architecture, pages 221-232, 2002.
17. T. Kistler and M. Franz. Continuous program optimization. ACM Transactions on Programming Languages and Systems, 25(4):500-548, July 2003.
18. M. H. Lipasti, B. R. Mestan, and E. Gunadi. Physical register inlining. In Proceedings of the 31st Annual International Symposium on Computer Architecture, 2004.
19. J. Martinez, J. Renau, M. Huang, M. Prvulovich, and J. Torrellas. Cherry: Checkpointed early resource recycling in out-of-order microprocessors. In Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002.
20. M. C. Merten, A. R. Trick, R. D. Barnes, E. M. Nystrom, C. N. George, J. C. Gyllenhaal, and W. mei W. Hwu. An architectural framework for run-time optimization. IEEE Transactions on Computers, 50(6):567-589, June 2001.
21. A. Moshovos and G. S. Sohi. Speculative memory cloaking and bypassing. In Proceedings of the 32nd Annual International Symposium on Microarchitecture, 1999.
22. M. Moudgill, K. Pingali, and S. Vassiliadis. Register renaming and dynamic speculation: An alternative approach. In Proceedings of the 26th Annual International Symposium on Microarchitecture, pages 202-213, 1993.
23. S. Önder and R. Gupta. Load and store reuse using register file contents. In Proceedings of the 15th International Conference on Supercomputing, pages 289-302, 2001.
24. V. Petric, A. Bracy, and A. Roth. Three extensions to register integration. In Proceedings of the 35th Annual International Symposium on Microarchitecture, pages 37-47, 2002.
25. V. Petrie, T. Sha, and A. Roth. RENO: A rename-based instruction optimizer. Technical Report MS-CIS-04-28, University of Pennsylvania, December 2004.
26. D. Ponomarev, G. Kucuk, O. Ergin, and K. Chose. Isolating short-lived operands for energy reduction. IEEE Transactions on Computers, 53(6):697-709, June 2004.
27. G. S. Tyson and T. M. Austin. Memory renaming: Fast, early and accurate processing of memory communication. International Journal of Parallel Programming, 27(5):357-380, 1999.
28. 2 Conference, pages 15-24, October 2004.