Putting the fill unit to work: Dynamic optimizations for trace cache microprocessors

Proceedings of the Annual International Symposium on Microarchitecture

Volumn , Issue , 1998, Pages 173-181

  Friendly, Daniel Holmes ^a   Patel, Sanjay Jeram ^a   Patt, Yale N ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; MICROPROCESSOR CHIPS; MICROPROGRAMMING; OPTIMIZATION; RESPONSE TIME (COMPUTER SYSTEMS); STORAGE ALLOCATION (COMPUTER);

TRACE CACHE MICROPROCESSORS;

REDUCED INSTRUCTION SET COMPUTING;

EID: 0032312214     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)