A dynamic test compaction procedure for high-quality path delay testing

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2006, Issue , 2006, Pages 348-353

  Fukunaga, Masayasu ^a   Kajihara, Seiji ^b   Wen, Xiaoqing ^b   Maeda, Toshiyuki ^c   Hamada, Shuji ^c   Sato, Yasuo ^c  

^a FUJITSU LABORATORIES LTD   (Japan)

^b KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

^c Academic Research Center   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; DELAY CIRCUITS; FAILURE ANALYSIS; SET THEORY;

DELAY FAULTS; DYNAMIC TESTS; TEST PATTERNS; TEST QUALITY;

INTEGRATED CIRCUIT TESTING;

EID: 33748586209     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118388     Document Type: Conference Paper

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