Path selection and pattern generation for dynamic timing analysis considering power supply noise effects

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2000-January, Issue , 2000, Pages 493-496

  Liou, Jing Jia ^a   Krstić, Angela ^a   Jiang, Yi Min ^b   Cheng, Kwang Ting ^a  

^a University of California   (United States)

^b SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; COMPUTER SIMULATION; CROSSTALK; ELECTRIC POWER SUPPLIES TO APPARATUS; GENETIC ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; MONTE CARLO METHODS; PROBABILITY DENSITY FUNCTION; SPURIOUS SIGNAL NOISE;

CIRCUIT PERFORMANCE; DEEP SUB-MICRON DESIGNS; DYNAMIC TIMING ANALYSIS; INPUT PATTERNS; PATTERN GENERATION; POWER-SUPPLY NOISE; PROPAGATION DELAYS; TIMING ANALYSIS;

COMPUTER AIDED DESIGN;

DEEP SUBMICRON DESIGN; DYNAMIC TIMING ANALYSIS; PATH GENERATION; PATH SELECTION; STATISTICAL TIMING ANALYSIS;

EID: 0034474847     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896521     Document Type: Conference Paper

References (12)

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