A critical path selection method for delay testing

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 232-241

  Padmanaban, Saravanan ^a   Tragoudas, Spyros ^b  

^a INTEL CORPORATION   (United States)

^b SOUTHERN ILLINOIS UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY TESTING; NANOMETER TECHNOLOGY; PATH DELAY FAULTS (PDF); SWITCHING NOISE;

COMPUTER WORKSTATIONS; CONSTRAINT THEORY; FAILURE ANALYSIS; GATES (TRANSISTOR); STANDARDS; TESTING;

NETWORKS (CIRCUITS);

EID: 18144399346     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)

1. Bhattacharya D., Agrawal P. and Agrawal V.D., Test Generation for Path Delay Faults using Binary Decision Diagrams, IEEE Trans. on Computers, vol. 44, no. 3, Mar. 1995, pp. 434-447.
2. Borkar S., et al., Parameter variations and impact on circuits and microarchitecture, Design Automation Conference, June 2003, pp. 338-342.
3. Cheng K.T and Chen H.C., Classification and Identification of Nonrobust Untestable Path Delay Faults, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, Aug. 1996, pp. 845-853.
4. Eppstein D., Finding the k Shortest Paths, IEEE Symp. Foundations of Computer Science, Santa Fe, 1994, pp. 154-165.
5. Fuchs K., Pabst M. and Rössel T., RESIST: A Recursive TestPattern Generation Algorithm for Path Delay Faults considering Various Test Classes, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 12, Dec. 1994, pp. 1550-1561.
6. Heragu K., Patel J.H. and Agrawal V.D., Fast identification of untestable delay faults using implications, Proc. International Conference on CAD, 1997, pp. 642-647.
7. Hitchcock R.B., Smith G.L. and Cheng D.D., Timing Analysis of Computer Hardware, IBM journal of Research and Development, January 1982, pp. 100-105.
8. Hulgaard H., Williams P.F. and Andersen H.R., Boolean Equivalence Checking of Combinational Circuits using Boolean Expression Diagrams, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 7, Jul. 1999, pp. 903-917.
9. Kirkpatrick T.I., and Clark N.R., PERT as an Aid to Logic Design, IBM journal of Research and Development, March 1966, pp. 135-141.
10. Li Z.C., Brayton R.K., Min Y., Efficient Identification of Non-Robustly Untestable Path Delay Faults, Proc. Internation Test Conference, 1997, pp. 992997.
11. Marques Silva J.P., Sakallah K.A, Grasp: A search algorithm for propositional satisfiability, IEEE Transactions on Computers, vol. 48, no. 5, pp. 506-521.
12. McGeer P.C., Saldanha A., Stephan P.R., Brayton R.K and Sangiovanni-Vincentelli A.L., Timing Analysis and Delay Fault Test Generation using Path Recursive Functions, Proc. of International Conference on Computer Aided Design, 1991, pp.180-183.
13. Michael M., Tragoudas S., ATPG Tools for Path Delay Faults at the Functional Level, ACM Transactions on Design Automation of Electronic Systems, vol. 7, no. 1, pp. 35-37, 2002.
14. Minato S.I, Zero-Suppressed Binary Decision Diagrams, Proc. Design Automation Conference, 1995.
15. Murakami A., Kajihara S., Sasao,T., Pomeranz I., Reddy S.M., Selection of Potentially Testable Path Delay Faults for Test Generation Proc. International Test Conference, 2000, pp. 376-384.
16. Padmanaban S., Michael M. and Tragoudas S., Exact Path Delay Fault Coverage with Fundamental Zero-Suppressed BDD Operations, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Mar. 2003, pp. 305-316.
17. Papadimitriou C.H and Steiglitz K., Combinatorial Optimization: Algorithms and Complexity, Dover Publishers, July 1998.
18. Pomeranz I. and Reddy S.M., SPACES-ACE: Simulator for Path Delay Faults, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no.2, Feb. 1994, pp. 254-263.
19. Shao Y., Reddy S.M., Kajihara S. and Pomeranz I., An Efficient Method to Identify Untestable Path Delay Faults, Proc. Asian Test Symposium, 2001.
20. Tafertshofer P., Ganz A., Antreich K.J., IGRAINE - An Implication GRaph bAsed engINE for Fast Implication, Justification, and Propagation, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, August 2000.
21. Tekumalla, R.C. and Menon, P.R., Identification of primitive faults in combinational and sequential circuits, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 12, December 2001, pp. 1426-1442.