Compact two-pattern test set generation for combinational and full scan circuits

IEEE International Test Conference (TC)

Volumn , Issue , 1998, Pages 944-953

  Hamzaoglu, Ilker ^a   Patel, Janak H ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC COMPACTION ALGORITHMS; ESSENTIAL FAULT REDUCTION (EFR); REDUNDANT VECTOR ELIMINATION (RVE);

ALGORITHMS; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; VECTORS;

COMBINATORIAL CIRCUITS;

EID: 0032317507     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.1998.743288     Document Type: Conference Paper

References (19)