Test enrichment for path delay faults using multiple sets of target faults

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2002, Pages 722-729

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^b  

^a PURDUE UNIVERSITY   (United States)

^b UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LONGEST PATH; MULTIPLE SET; PATH DELAY FAULT; PATH LENGTH; TARGET FAULTS; TEST GENERATION PROCEDURE; TEST SETS;

EXHIBITIONS;

TESTING;

EID: 13244280956     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998379     Document Type: Conference Paper

References (13)

1. G. L. Smith, "Model for Delay Faults Based Upon Paths", in Proc. 1985 Intl. Test Conf., pp. 342-349.
2. I. Pomeranz and S. M. Reddy, "An Efficient Non-Enumerative Method to Estimate Path Delay Fault Coverage", in Proc. Intl. Conf. on Computer-Aided Design, 1992, pp. 560-567.
3. W.-N. Li, S. M. Reddy and S. K. Sahni, "On path Selection in Combinational Logic Circuits", IEEE Trans. on Computer-Aided Design, Jan. 1989, pp. 56-63.
4. L. N. Reddy, "Compact Test Sets for Digital Logic Circuits", Ph.D. Thesis, ECE Dept., University of Iowa, August 1992.
5. S. Bose, P. Agrawal and V. D. Agrawal, "Generation of Compact Delay Tests by Multiple Path Activation", in Proc. 1993 Intl. Test Conf., Oct. 1993, pp. 714-723.
6. J. Saxena and D. K. Pradhan, "A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits", in Proc. 1993 Intl. Test Conf., Oct. 1993, pp. 724-733.
7. M. H. Schultz, K. Fuchs and F. Fink, "Advanced Automatic Test Pattern Generation Techniques for Path Delay Faults", in Proc. Intl. Symp. on Fault-Tolerant Computing, June 1989, pp. 44-51.
8. P. Goel and B. C. Rosales, "Test Generation & Dynamic Compaction of Tests", in Digest of Papers 1979 Test Conf., Oct. 1979, pp. 189-192.
9. K. Fuchs, F. Fink and M. H. Schulz, "DYNAMITE: An Efficient Automatic Test Pattern Generation for Path Delay Faults", IEEE Trans. on Computer-Aided Design, Oct. 1991, pp. 1323-1335.
10. K.-T. Cheng and H.-C. Chen, "Delay Testing for Nonrobust Untestable Circuits", in Proc. Intl. Test Conf., Oct. 1993, pp. 954-961.
11. U. Sparmann, D. Luxenburger, K.-T. Cheng, and S. M. Reddy, "Fast Identification of Robust Dependent Path Delay Faults", in Proc. Design Autom. Conf., June 1995, pp. 119-125.
12. S. Kajihara, K. Kinoshita, I. Pomeranz and S. M. Reddy, "A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths", in Proc. 1997 VLSI Design Conf., Jan. 1997, pp. 82-87.
13. I. Pomeranz and S. M. Reddy, "On Synthesis-for-Testability of Combinational Logic Circuits", in Proc. 32nd Design Autom. Conf., June 1995, pp. 126-132.