A Postprocessing procedure of test enrichment for path delay faults

Proceedings of the Asian Test Symposium

Volumn , Issue , 2004, Pages 448-453

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^b  

^a PURDUE UNIVERSITY   (United States)

^b UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUITS; PATH DELAY FAULTS; TARGET FAULTS; TEST COMPACTION HEURISTICS;

COMPUTATIONAL METHODS; COMPUTER SIMULATION; CRITICAL PATH ANALYSIS; ERROR ANALYSIS; FAILURE ANALYSIS; FORMAL LOGIC; HEURISTIC METHODS; MATHEMATICAL MODELS; QUALITY ASSURANCE; SET THEORY;

INTEGRATED CIRCUITS;

EID: 13244277449     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2004.14     Document Type: Conference Paper

References (16)

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