On selecting testable paths in scan designs

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 19, Issue 4, 2003, Pages 447-456

  Shao, Yun ^a   Reddy, Sudhakar M ^a   Pomeranz, Irith ^b   Kajihara, Seiji ^c  

^a UNIVERSITY OF IOWA   (United States)

^b PURDUE UNIVERSITY   (United States)

^c KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Delay fault; Delay testing; Path delay fault; Path selection; Testable path

Indexed keywords

ALGORITHMS; DEFECTS; DELAY CIRCUITS; DESIGN FOR TESTABILITY; FAILURE ANALYSIS; INTEGRATED CIRCUIT MANUFACTURE; POLYNOMIALS; SPURIOUS SIGNAL NOISE;

BENCHMARK CIRCUITS; BROADSIDE TESTING; DELAY ANALYSIS; DELAY FAULT; DELAY TESTING; SCAN DESIGNS;

INTEGRATED CIRCUIT TESTING;

EID: 0042475652     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1024648227669     Document Type: Article

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