High quality robust tests for path delay faults

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1997, Pages 88-93

  Chen, Liang Chi ^a   Gupta, Sandeep K ^a   Breuer, Melvin A ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; LOGIC CIRCUITS; OPTIMIZATION;

PATH DELAY FAULTS; ROBUST TESTS;

INTEGRATED CIRCUIT TESTING;

EID: 0030645110     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)