Path delay test compaction with process variation tolerance

Proceedings - Design Automation Conference

Volumn , Issue , 2005, Pages 845-850

  Kajihara, Seiji ^a   Fukunaga, Masayasu ^a   Wen, Xiaoqing ^a   Maeda, Toshiyuki ^b   Hamada, Shuji ^b   Sato, Yasuo ^b  

^a KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

^b SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

Author keywords

Delay testing; Path delay fault; Process variation; Test compaction

Indexed keywords

ELECTRIC FAULT CURRENTS; LOGIC DEVICES; SPURIOUS SIGNAL NOISE;

DELAY TESTING; PATH DELAY FAULT; PROCESS VARIATION; TEST COMPACTION;

DELAY CIRCUITS;

EID: 27944446998     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dac.2005.193933     Document Type: Conference Paper

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