Modeling and reduction of gate leakage during behavioral synthesis of NanoCMOS circuits

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2006, Issue , 2006, Pages 83-88

  Mohanty, Saraju P ^a   Kougianos, Elias ^a  

^a UNIVERSITY OF NORTH TEXAS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GATE LEAKAGE; NANOCMOS CIRCUITS; POWER DISSIPATION; TUNNELING CURRENTS;

ELECTRIC POWER UTILIZATION; ELECTRON TUNNELING; LEAKAGE CURRENTS; MATHEMATICAL MODELS; NANOTECHNOLOGY; SILICA;

CMOS INTEGRATED CIRCUITS;

EID: 33748540028     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2006.118     Document Type: Conference Paper

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