Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies

European Solid-State Circuits Conference

Volumn , Issue , 2003, Pages 313-316

  Rao, Rahul M ^a   Burns, Jeffrey L ^b   Brown, Richard B ^a  

^a Department of Ecology and Evolutionary Biology   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASSIGNMENT TECHNIQUE; CIRCUIT TECHNIQUES; CMOS TECHNOLOGY; DYNAMIC CIRCUITS; GATE-LEAKAGE CURRENT; LEAKAGE MINIMIZATION; SUB-THRESHOLD LEAKAGE; TOTAL POWER DISSIPATION;

CMOS INTEGRATED CIRCUITS; STATE ASSIGNMENT;

LEAKAGE CURRENTS;

EID: 33748537450     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2003.1257135     Document Type: Conference Paper

References (5)

1. International Technology Roadmap for Semiconductors, 2001 Edition, http://public. itrs. net/Files/2001lTRS/Home. html
2. T. Inukai, et. al, "Boosted Gate MOS (BGMOS): Device/ Circuit Cooperation Scheme to Achieve Leakage-Free Giga-Scale Integration, " Proc. CICC 2000, pp. 409-412.
3. F. Hamzaoglu and M. Stan, "Circuit-Level Techniques to Control Gate Leakage for sub-lOOnm CMOS, " Proc. ISLPED, pp. 60-63, Aug. 2002.
4. Y. Yeo, et. al, "Direct Tunneling Gate Leakage Current in Transistors with Ultrathin Silicon Nitride Gate Dielectric, " IEEE Electron Devices Letters, vol. 21, no. 11, pp. 540-542, Nov. 2000.
5. S. Mutoh, et. al, "1-V Power Supply High-Speed Digital Circuit Technology with Multi-Threshold Voltage CMOS, " IEEE Journal of Solid State Circuits, vol. 30, no. 8, pp. 847-854, Aug. 1995.