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Volumn , Issue , 2003, Pages 313-316

Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies

Author keywords

[No Author keywords available]

Indexed keywords

ASSIGNMENT TECHNIQUE; CIRCUIT TECHNIQUES; CMOS TECHNOLOGY; DYNAMIC CIRCUITS; GATE-LEAKAGE CURRENT; LEAKAGE MINIMIZATION; SUB-THRESHOLD LEAKAGE; TOTAL POWER DISSIPATION;

EID: 33748537450     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2003.1257135     Document Type: Conference Paper
Times cited : (17)

References (5)
  • 1
    • 84893748428 scopus 로고    scopus 로고
    • International Technology Roadmap for Semiconductors, 2001
    • International Technology Roadmap for Semiconductors, 2001 Edition, http://public. itrs. net/Files/2001lTRS/Home. html
  • 2
    • 0033719725 scopus 로고    scopus 로고
    • Boosted gate mos (bgmos): Device/ circuit cooperation scheme to achieve leakage-free giga-scale integration
    • T. Inukai, et. al, "Boosted Gate MOS (BGMOS): Device/ Circuit Cooperation Scheme to Achieve Leakage-Free Giga-Scale Integration, " Proc. CICC 2000, pp. 409-412.
    • (2000) Proc. CICC , pp. 409-412
    • Inukai, T.1
  • 3
    • 0036948939 scopus 로고    scopus 로고
    • Circuit-level techniques to control gate leakage for sub-loonm cmos
    • Aug
    • F. Hamzaoglu and M. Stan, "Circuit-Level Techniques to Control Gate Leakage for sub-lOOnm CMOS, " Proc. ISLPED, pp. 60-63, Aug. 2002.
    • (2002) Proc. ISLPED , pp. 60-63
    • Hamzaoglu, F.1    Stan, M.2
  • 4
    • 0034318446 scopus 로고    scopus 로고
    • Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric
    • Nov
    • Y. Yeo, et. al, "Direct Tunneling Gate Leakage Current in Transistors with Ultrathin Silicon Nitride Gate Dielectric, " IEEE Electron Devices Letters, vol. 21, no. 11, pp. 540-542, Nov. 2000.
    • (2000) IEEE Electron Devices Letters , vol.21 , Issue.11 , pp. 540-542
    • Yeo, Y.1
  • 5
    • 0029359285 scopus 로고
    • 1-v power supply high-speed digital circuit technology with multi-threshold voltage cmos
    • Aug
    • S. Mutoh, et. al, "1-V Power Supply High-Speed Digital Circuit Technology with Multi-Threshold Voltage CMOS, " IEEE Journal of Solid State Circuits, vol. 30, no. 8, pp. 847-854, Aug. 1995.
    • (1995) IEEE Journal of Solid State Circuits , vol.30 , Issue.8 , pp. 847-854
    • Mutoh, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.