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Volumn , Issue , 2003, Pages 313-316
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Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies
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Author keywords
[No Author keywords available]
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Indexed keywords
ASSIGNMENT TECHNIQUE;
CIRCUIT TECHNIQUES;
CMOS TECHNOLOGY;
DYNAMIC CIRCUITS;
GATE-LEAKAGE CURRENT;
LEAKAGE MINIMIZATION;
SUB-THRESHOLD LEAKAGE;
TOTAL POWER DISSIPATION;
CMOS INTEGRATED CIRCUITS;
STATE ASSIGNMENT;
LEAKAGE CURRENTS;
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EID: 33748537450
PISSN: 19308833
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/ESSCIRC.2003.1257135 Document Type: Conference Paper |
Times cited : (17)
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References (5)
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