Efficient compression of deterministic patterns into multiple PRPG seeds

Proceedings - International Test Conference

Volumn 2005, Issue , 2005, Pages 916-925

  Wohl, Peter ^a   Waicukauski, John A ^a   Patel, Sanjay ^a   DaSilva, Francisco ^a   Williams, T W ^a   Kapur, Rohit ^a  

^a SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; DATA COMPRESSION; DESIGN FOR TESTABILITY; ELECTRONIC EQUIPMENT TESTING; OPTIMIZATION;

DATA VOLUME; PSEUDO-RANDOM PATTERN GENERATOR (PRPG); SCAN CELLS; TEST PATTERN COUNT;

PATTERN RECOGNITION;

EID: 33748482074     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2005.1584057     Document Type: Conference Paper

References (24)

1. Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors (TTRS), 1999.
2. M. Abramovici, M. A. Breuer, A.D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, 1990.
3. E.B. Eichelberger, E. Lindbloom, J.A. Waicukauski, T.W. Williams, Structured Logic Testing, Prentice-Hall, 1991.
4. P.H. Bardell, W.H. McAnney, J. Savir, Built-in Test for VLSI: Pseudorandom Techniques, John Wiley & Sons, 1987.
5. P. Wohl, J.A. Waicukauski, S. Patel, M. Amin, "EfficientCompression and Application of Deterministic Patterns in a Logic BIST Architecture "Design Automation Conference 2003, pp. 566-569.
6. J. Rajski, J. Tyszer, M. Kassab, N. Mukherjee, R. Thompson, K.H. Tsai, A. Hertwig, N. Tamarapalli. G. Mrugalski, G. Eide, J. Qian, "Embedded Deterministic Test for Low Cost Manufacturing Test," International Test Conf. 2002, pp. 301-310.
7. P. Wohl, J.A. Waicukauski, S. Patel, M. Amin, "X-Tolerant Compression and Application of Scan-ATPG Patterns in a BIST Architecture," International Test Conference 2003, pp. 727-736.
8. PH. Bardell, W.H. McAnney, "Self-Testing of Multichip Logic Modules," International Test Conf. 1982, pp.200-204.
9. C. Barnhart, V Brunkhorst, F. Distler, O. Famsworth, B. Keller, B. Koenemann, "OPMISR: The Foundation for Compressed ATPG Vectors," International Test Conference 2001, pp. 748-757.
10. I. Pomeranz, S. Kundu, S.M. Reddy, "On Output Response Compression in the Presence of Unknown Output Values," Design Automation Conference 2002, pp. 255-258.
11. M. Naruse, I. Pomeranz, S.M. Reddy, S. Kundu, "On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding," International Test Conference 2003, pp. 1060-1068.
12. S. Mitra, K. S. Kim, "X-Compact An Efficient Response Compaction Technique for Test Cost Reduction," International Test Conference 2002, pp.311-320.
13. J. Rajski, J. Tyszer, C. Wang, S.M. Reddy, "Convolutional Compaction of Test Responses," International Test Conference 2003, pp. 745-754.
14. P. Wohl, J.A. Waicukauski, S. Patel, "Scalable Selector Architecture for X-Tolerant Deterministic BIST," Design Automation Conference 2004.
15. B. Könemann, "LFSR-Coded Test Patterns for Scan Designs," European Test Conference, Munich, 1991.
16. S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois, "Built-in Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers," IEEE Transactions on Computers, Vol. 44, No. 2, Feb. 1995.
17. S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich, "Pattern Generation for a Deterministic BIST Scheme," International Conference on Computer-Aided Design, 1995.
18. S. Hellebrand, S. Tarnick, J. Rajski, "Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feed-back Shift Registers," International Test Conf 2002, pp. 120-129.
19. S. Chiusano, S. DiCarlo, P. Prinetto, H.-J. Wunderlich, "On Applying the Set Covering Model to Reseeding," Design and Test Europe, 2001.
20. N.C. Lai, S.J. Wang, "A Reseeding Technique for LFSR-Based BIST Applications," Asian Test Symposium 2002, pp. 200-205.
21. A.A. Al-Yamani, E.J. McCluskey, "Seed Encoding with LFSRs and Cellular Automata," Design Automation Conference 2003, pp. 560-565.
22. B. Koenemann, C. Barnhart, B. Keller, T. Snethen, O. Famsworth, D. Wheater, "A SmartBIST Variant with Guaranteed Encoding," Asian Test Symposium 2001, pp. 325-330.
23. H.Vranken, F. Hapke, S. Rogge, D.Chindamo, E.Volkerink,"ATPG padding and ATE Vector Repeat per Port for Reducing Test Data Volume", International Test Conference 2003, pp. 1069-1078.
24. P. Wohl, J.A. Waicukauski, "Optimizing the Flattened Test-Generation Model for Very Large Designs," International Test Conference 2000, pp. 681-690.