A reseeding technique for LFSR-based BIST applications

Proceedings of the Asian Test Symposium

Volumn 2002-January, Issue , 2002, Pages 200-205

  Lai, Nan Cheng ^a   Wang, Sying Jyan ^a  

^a NATIONAL CHUNG HSING UNIVERSITY   (Taiwan)

Author keywords

Built in self test; Testing

Indexed keywords

INTEGRATED CIRCUIT TESTING; TESTING;

BENCHMARK CIRCUIT; DESIGN METHODOLOGY; HARD-TO-DETECT FAULTS; HARDWARE OVERHEADS; MULTIPLE SEEDS; SPECIFIC STATE; TEST APPLICATION TIME; TEST PATTERN GENERATOR;

BUILT-IN SELF TEST;

EID: 0042193609     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2002.1181711     Document Type: Conference Paper

References (8)

1. V. D. Agrawal, CR. Kime, and K. K. Saluja, "A tutorial on Built-In Self-Test, part 1: principles," IEEE Design & Test Computers, pp. 73-82, Mar. 1993.
2. V. D. Agrawal, CR. Kime, and K. K. Saluja, "A tutorial on Built-In Self-Test, part 2: applications," IEEE Design & Test Computers, pp. 69-77, June 1993.
3. J. Savir and W. H. McAnney, "A multiple seed linear feedback shift register," IEEE Trans. on Computers, Vol. 41, No. 2, pp. 250-252, Feb. 1992.
4. J. Venkataraman, J. Rajski, S. Tarnick, and S. Hellebrand, "An efficient BIST scheme based on reseeding or multiple polynomial linear feedback shift registers," in Proc. Int'l Conf Computer-Aided Design, pp. 572-577, Nov. 1993.
5. j. Hellebrand. J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, "Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers," IEEE Trans. on Computers, Vol. 44, No. 2, pp. 223-233, Feb. 1995.
6. J. K. Mukund, E. J. McCluskey, and T. R. N. Rao, "An apparatus for pseudo-deterministic testing," in Proc. VLSI Test Symp. , pp. 125-131, Apr.-May 1995.
7. S. Chiusano, P. Prinetto, and H. J. Wunderlich, "Non-intrusive BIST for system-on-a-chip. " in Proc. Int'l Test Conf, pp. 644-651, Oct. 2000.
8. E. Kalligeros, X. Kavousianos, D. Bakalis, and D. Nikolos, "A new reseeding technique for LFSR-hased test pattern generation," in Proc. Int'l On-Line Testing Workshop, pp. 80-86, 2001.