Optimizing the flattened test-generation model for very large designs

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 681-690

  Wohl, Peter ^a   Waicukauski, John ^a  

^a SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUIT LAYOUT; LARGE SCALE SYSTEMS; OPTIMIZATION; SEMICONDUCTOR DEVICE MODELS;

AUTOMATIC TEST PATTERN GENERATION; FAULT SIMULATOR; FINAL MEMORY USAGE;

DESIGN FOR TESTABILITY;

EID: 0034484259     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (26)