Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 7, 2006, Pages 707-716

  Zhu, Xinping ^b   Qin, Wei ^c   Malik, Sharad ^a,d  

^a IEEE   (United States)

^b Northeastern University ^*  (United States)

^c Boston University College of Engineering   (United States)

^d Princeton University   (United States)

Author keywords

Bus; Design exploration; Multiprocessor system; On chip communication architecture (OCA); Packet switching network; Retargetable simulation; Simulator synthesis

Indexed keywords

BUS; DESIGN EXPLORATION; MULTIPROCESSOR SYSTEM; ON-CHIP COMMUNICATION ARCHITECTURE (OCA); PACKET-SWITCHING NETWORK; RETARGETABLE SIMULATION; SIMULATOR SYNTHESIS;

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; INFORMATION ANALYSIS; MATHEMATICAL MODELS; MULTIPROCESSING SYSTEMS; OPTIMIZATION; PATTERN RECOGNITION; SIMULATORS; SOFTWARE PROTOTYPING;

COMMUNICATION;

EID: 33746917205     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2006.878266     Document Type: Conference Paper

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