Low hardware overhead scan based 3-weight weighted random BIST

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 868-877

  Wang, Seongmoon ^a  

^a NEC LABORATORIES AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATA THEORY; BENCHMARKING; BUILT-IN SELF TEST; SHIFT REGISTERS;

BENCHMARK CIRCUITS; RANDOM PATTERN RESISTANT CIRCUITS;

INTEGRATED CIRCUIT TESTING;

EID: 0035681202     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)

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6. How to do weighted random testing for BIST
7. Pattern generation for a deterministic BIST scheme
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10. Cube-contained random patterns and their application to the complete testing of synthesized multi-level circuits
11. 3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits
12. Deterministic pattern generation for weighted random pattern testing
13. A Pragmatic approach to the design of self-testing circuits
14. SIS: A system for sequential circuit synthesis
15. Constructive multi-pahse test point insertion for scan-based BIST
16. Altering a pseudo-random bit sequence for scan-based BIST
17. Efficient test-point selection for scan-based BIST
18. A method for generating weighted random test patterns