Minimal buffer insertion in clock trees with skew and slew rate constraints

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 4, 1997, Pages 333-342

  Téllez, Gustavo E ^a  

^a IBM   (United States)

Author keywords

Buffered clock tree; Clock phase delay; Clock skew; Clock slew rate

Indexed keywords

ALGORITHMS; CLOCKS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; CONSTRAINT THEORY; PARAMETER ESTIMATION; TREES (MATHEMATICS);

BUFFER INSERTION ALGORITHMS; BUFFERED CLOCK TREE; SOFTWARE PACKAGE SPICE;

BUFFER CIRCUITS;

EID: 0031124218     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.602470     Document Type: Article

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