Buffered clock tree for high quality IC design

Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004

Volumn , Issue , 2004, Pages 381-386

  Chaturvedi, Rishi ^a   Hu, Jiang ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; ELECTRIC CLOCKS; ELECTRIC LOADS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; ROUTERS; SPURIOUS SIGNAL NOISE; SWITCHING;

POWER CONSUMPTION; POWER SUPPLY NOISE; PROCESS VARIATIONS; SYNCHRONOUS DIGITAL INTEGRATED CIRCUITS;

VLSI CIRCUITS;

EID: 2942637949     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2004.1283704     Document Type: Conference Paper

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