메뉴 건너뛰기




Volumn 2005, Issue , 2005, Pages 325-336

Implementing Kilo-Instruction multiprocessors

Author keywords

[No Author keywords available]

Indexed keywords

CONSISTENCY HARDWARE; MEMORY COHERENCE; MULTIPROCESSORS; SOFTWARE SUPPORT;

EID: 33745683392     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PERSER.2005.1506430     Document Type: Conference Paper
Times cited : (26)

References (30)
  • 2
    • 2342487209 scopus 로고    scopus 로고
    • Large virtual ROBs by processor checkpointing
    • UPC, Spain, July
    • A. Cristal, M. Valero, J. Llosa, and A. Gonzalez, "Large virtual ROBs by processor checkpointing", Tech. Rep. UPC-DAC-2002-39, UPC, Spain, July 2002
    • (2002) Tech. Rep. , vol.UPC-DAC-2002-39
    • Cristal, A.1    Valero, M.2    Llosa, J.3    Gonzalez, A.4
  • 4
    • 0242370931 scopus 로고    scopus 로고
    • Kilo-instruction processors
    • Intl. Symp. on High Performance Computers, October 2003
    • A. Cristal, D. Ortega, J. Llosa, and M. Valero, "Kilo-instruction processors", In Intl. Symp. on High Performance Computers, October 2003. LNCS 2858, 2003.
    • (2003) LNCS , vol.2858
    • Cristal, A.1    Ortega, D.2    Llosa, J.3    Valero, M.4
  • 7
    • 22944446075 scopus 로고    scopus 로고
    • Kilo-instruction processors: Overcoming the memory wall
    • To be published May/June
    • A. Cristal et al., "Kilo-instruction Processors: Overcoming the Memory Wall", To be published on IEEE Micro Magazine, Vol. 25, No. 3, May/June, 2005.
    • (2005) IEEE Micro Magazine , vol.25 , Issue.3
    • Cristal, A.1
  • 9
    • 0029221752 scopus 로고
    • Internal organization of the alpha 21164, a 300-MHz 64-bit quad-issue CMOS RISC microprocessor
    • J. H. Edmondson, et al., "Internal organization of the Alpha 21164, a 300-MHz 64-bit quad-issue CMOS RISC microprocessor", Digital Technical Journal, Vol, 7, No. 1, 1995, pp. 119-135.
    • (1995) Digital Technical Journal , vol.7 , Issue.1 , pp. 119-135
    • Edmondson, J.H.1
  • 10
    • 4143054872 scopus 로고    scopus 로고
    • A first glance at kilo-instruction based multiprocessors
    • Ischia, Italy, April
    • st Conf. on Computing Frontiers, pp. 212-221, Ischia, Italy, April 2004.
    • (2004) st Conf. on Computing Frontiers , pp. 212-221
    • Galluzzi, M.1
  • 11
    • 0002833108 scopus 로고
    • Memory consistency and event ordering in scalable shared-memory multiprocessors
    • th ISCA, 1990.
    • (1990) th ISCA
    • Gharachorloo, K.1
  • 12
    • 0004029273 scopus 로고
    • Cache consistency and sequential consistency
    • SCI Committee, March
    • J. R. Goodman, "Cache Consistency and Sequential Consistency", Tech.Rep. no.61, SCI Committee, March 1989
    • (1989) Tech.Rep. No.61 , vol.61
    • Goodman, J.R.1
  • 15
    • 33745687533 scopus 로고    scopus 로고
    • Coherence decoupling: Making use of incoherence
    • October
    • J. Huh et al., "Coherence Decoupling: Making Use of Incoherence", In Proc. of the 11th ASPLOS, October 2004
    • (2004) Proc. of the 11th ASPLOS
    • Huh, J.1
  • 17
    • 0018518477 scopus 로고
    • How to make a multiprocessor computer that correctly executes multiprocess programs
    • L. Lamport, "How to make a Multiprocessor Computer that Correctly Executes Multiprocess Programs", IEEE Transactions on Computers, C-28(9):690-691, 1979.
    • (1979) IEEE Transactions on Computers , vol.C-28 , Issue.9 , pp. 690-691
    • Lamport, L.1
  • 20
  • 24
    • 84955506994 scopus 로고    scopus 로고
    • Runahead execution: An alternative to very large instruction windows for out-of-order processors
    • th HPCA, pp. 129-140, 2003
    • (2003) th HPCA , pp. 129-140
    • Mutlu, O.1
  • 25
    • 0003074246 scopus 로고    scopus 로고
    • An evaluation of memory consistency models for shared-memory systems with ILP processors
    • October
    • V. S. Pai, P. Ranganathan, S. V. Adve, and T. Karton, "An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors", In Proc. Of the 7th ASPLOS, October 1996
    • (1996) Proc. of the 7th ASPLOS
    • Pai, V.S.1    Ranganathan, P.2    Adve, S.V.3    Karton, T.4
  • 26
    • 0035694494 scopus 로고    scopus 로고
    • Speculative lock elision: Enabling highly-concurrent multithreaded execution
    • Dec.
    • R. Rajwar, and J. R. Goodman, "Speculative Lock Elision: Enabling Highly-Concurrent Multithreaded Execution", In Proc. of 34th Intl. Symp. on Microarchitecture, pp.294-305, Dec. 2001.
    • (2001) Proc. of 34th Intl. Symp. on Microarchitecture , pp. 294-305
    • Rajwar, R.1    Goodman, J.R.2
  • 30
    • 0009552847 scopus 로고    scopus 로고
    • SafetyNet: Improving the availability of shared memory multiprocessors with global checkpoint/recovery
    • June
    • D. J. Sorin et al., "SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint/recovery", In Proc. of the 29th ISCA, June 2002.
    • (2002) Proc. of the 29th ISCA
    • Sorin, D.J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.