Exploiting mixed-mode parallelism for matrix operations on the HERA architecture through reconfiguration

IEE Proceedings: Computers and Digital Techniques

Volumn 153, Issue 4, 2006, Pages 249-260

  Wang, X ^a   Ziavras, S G ^b  

^a Villanova University   (United States)

^b NEW JERSEY INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATION THEORY; COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC DESIGN; SCHEDULING;

FLOATING-POINT UNITS (FPU); LU FACTORIZATION; MATRIX-MATRIX MULTIPLICATION (MMM); SPARSE DOUBLY-BORDERED-BLOCK-DIAGONAL (DBBD) MATRICES;

PARALLEL PROCESSING SYSTEMS;

EID: 33745683356     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:20045136     Document Type: Article

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