Scalable and modular algorithms for floating-point matrix multiplication on FPGAs

Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM)

Volumn 18, Issue , 2004, Pages 1297-1306

  Zhuo, Ling ^a   Prasanna, Viktor K ^a  

^a University of Southern California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATION THEORY; MATRIX ALGEBRA; MICROPROCESSOR CHIPS; OPTIMIZATION; PROGRAM PROCESSORS;

FLOATING-POINT UNITS; LINEAR ARRAY ARCHITECTURE; PROCESSING ELEMENTS (PE);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 12444290912     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

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