Parallel LU factorization of sparse matrices on FPGA-based configurable computing engines

Concurrency and Computation: Practice and Experience

Volumn 16, Issue 4, 2004, Pages 319-343

  Wang, Xiaofang ^a   Ziavras, Sotirios G ^a  

^a NEW JERSEY INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

FPGA; Hardware design; LU factorization; Matrix inversion; Parallel processing; SOPC SOC

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; COMPUTER WORKSTATIONS; FIELD PROGRAMMABLE GATE ARRAYS; LINEAR EQUATIONS; MATRIX ALGEBRA; SILICON ON INSULATOR TECHNOLOGY; SUPERCOMPUTERS;

CONFIGURABLE COMPUTING; HARDWARE DESIGN; LU FACTORIZATION; MATRIX INVERSION; SPARSE MATRICES; SYSTEM ON A PROGRAMMABLE CHIP;

PARALLEL PROCESSING SYSTEMS;

EID: 1842533207     PISSN: 15320626     EISSN: None     Source Type: Journal    
DOI: 10.1002/cpe.748     Document Type: Article

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