Practical repeater insertion for low power: What repeater library do we need?

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 5, 2006, Pages 917-924

  Liu, Xun ^a   Peng, Yuantao ^a   Papaefthymiou, Marios C ^b  

^a North Carolina State University   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Interconnect; Repeater insertion low power

Indexed keywords

COMPUTATION THEORY; DIGITAL LIBRARIES; FAULT TOLERANT COMPUTER SYSTEMS; OPTICAL INTERCONNECTS; PROBLEM SOLVING;

OPTIMAL REPEATER NUMBER; REPEATER INSERTION ALGORITHM; REPEATER INSERTION LOW POWER; REPEATER LIBRARY;

ALGORITHMS;

EID: 33646410712     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.855968     Document Type: Conference Paper

References (29)

1. V. Adler and E. G. Friedman, "Repeater design to reduce delay and power in resistive interconnect," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 5, pp. 607-616, May 1998.
2. C. J. Alpert and A. Devgan, "Wire segmenting for improved buffer insertion," in Proc. Design Automation Conf., Sacramento, CA, Jun. 1997, pp. 588-593.
3. C. J. Alpert, A. Devgan, and S. T. Quay, "Buffer insertion with accurate gate and interconnect delay computation," in Proc. Design Automation Conf., New Orleans, LA, Jun. 1999, pp. 479-184.
4. C. J. Alpert, R. G. Gandham, J. L. Neves, and S. T. Quay, "Buffer library selection," in Proc. Int. Conf. Computer Design, Austin, TX, Sep. 2000, pp. 221-226.
5. C. J. Alpert, J. Hu, S. S. Sapatnekar, and P. G. Villarrubia, "A practical methodology for early buffer and wire resource allocation," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 22, no. 5, pp. 573-583, May 2003.
6. H. B. Bakoglu, Circuits, Interconnects, and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990.
7. K. Banerjee and A. Mehrotra, "A power-optimal repeater insertion methodology for global interconnects in nanometer designs," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 49, no. 11, pp. 2001-2007, Nov. 2002.
8. C.-C. N. Chu and D. F. Wong, "Closed form solution to simultaneous buffer insertion/sizing and wire sizing," in Proc. Int. Symp. Physical Design, Napa Valley, CA, Apr. 1997, pp. 192-197.
9. _, "An efficient and optimal algorithm for simultaneous buffer and wire sizing," IEEE Trans. Comput.-Aided Des. Imegr. Circuits Syst., vol. 18, no. 9, pp. 1297-1304, Sep. 1999.
10. _, "A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing." IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 18, no. 6, pp. 787-798, Jun. 1999.
11. J. Cong, L. He, C. K. Koh, and P. H. Madden, "Performance optimization of VLSI interconnect layout," Integr. VLSI J., vol. 21, no. 1, pp. 1-94, Jan. 1996.
12. J. Cong, T. Kong, and D. Z. Pan, "Buffer block planning for interconnect-driven floorplanning," in Proc. Int. Conf. Computer-Aided Design (ICCAD), San Jose, CA, Nov. 1999, pp. 358-363.
13. G. S. Garcea, N. P. van der Meijs, and R. H. Otten, "Simultaneous analytical area and power optimization for repeater insertion," in Proc. Int. Conf. Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2003, pp. 568-573.
14. N. Hedenstierna and K. O. Jeppson, "CMOS circuit speed and buffer optimization," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. CAD-6, no. 2, pp. 270-280, Feb. 1987.
15. [15[ M. Rang, W. Dai, T. Dillinger, and D. LaPotin, "Delay bounded buffered tree construction for timing driven floorplanning," in Proc. Int. Conf. Computer-Aided Design (ICCAD). San Jose, CA, Nov. 1997, pp. 707-712.
16. P. Kapur, G. Chandra, and K. C. Saraswat, "Power estimation in global interconnect and its reduction using a novel repeater optimization methodology," in Proc. Design Automation Conf., New Orleans, LA, Jun, 2002, pp. 461-466.
17. W. Liao and L. He, "Full-chip interconnect power estimation and simulation considering concurrent repeater and flip-flop insertion," in Proc. Int. Conf. Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2003, pp. 574-580.
18. J. Lillis, C. K. Cheng, and T.-T. Y. Lin, "Optimal wire sizing and buffer insertion for low power and a generalized delay model," J. Solid-State Circuits, vol. 31, no. 3, pp. 437-147, Mar. 1996.
19. X. Liu, Y. Peng, and M. C. Papaefthymiou, "Practical repeater insertion for low power: What repeater library do we need?" in Proc. Design Automation Conf., San Diego, CA, Jun. 2004, pp. 30-35.
20. L. P. P. P. van Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay," in Proc. Int. Symp. Circuits and Systems, New Orleans, LA, 1990, pp. 865-868.
21. A. Nalamalpu and W. P. Burleson, "Repeater insertion in deep sub-micron CMOS: Ramp-based analytical model and placement sensitivity analysis," in Proc. Int. Symp. Circuits and Systems, Geneva, Switzerland, May 2000, pp. 766-169.
22. _, "A practical approach to DSM repeater insertion: Satisfying delay constraints while minimizing area and power," in Proc. IEEE Int. Application-Specified Integrated. Circuit/System-on-a-Chip (ASIC/SOC) Conf., Arlington, VA, Sep. 2001, pp. 152-156.
23. M. Nekili and Y. Savaria, "Optimal methods of driving interconnections in VLSI circuits," in Proc. Int. Symp. Circuits and Systems. San Diego, CA, May 1993, pp. 21-24.
24. T. Okamoto and J. Cong, "Buffered Steiner tree construction with wire sizing for interconnect layout optimization," in Proc. Int. Conf. Computer-Aided Design (ICCAD), San Jose, CA, 1996, pp. 44-19.
25. R. Otten, "Global wires harmful?" in Int. Symp. Physical Design, Monterey, CA, Apr. 1998, pp. 104-109.
26. D. Sylvester and K. Keutzer, "Getting to the bottom of deep submicron," in Proc. Int. Conf. Computer-Aided Design (ICCAD), San Jose, CA, Nov. 1998, pp. 203-211.
27. _, "A global wiring paradigm for deep submicron design," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 19, no. 2, pp. 242-252, Feb. 2000.
28. C. Y. Wu and M. Shiau, "Delay models and speed improvement techniques for RC tree interconnections among small geometry CMOS VLSI," J. Solid-State Circuits, vol. 25, no. 10, pp. 1247-1256, Oct. 1990.
29. H. Zhou, D. F. Wong, I.-M. Liu, and A. Aziz, "Simultaneous routing and buffer insertion with restrictions on buffer locations," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 19, no. 7, pp. 819-824, Jul. 2000.