A practical methodology for early buffer and wire resource allocation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 5, 2003, Pages 573-583

  Alpert, Charles J ^a   Hu, Jiang ^b   Sapatnekar, Sachin S ^c   Villarubia, Paul G ^a  

^a IBM   (United States)

^b TEXAS A AND M UNIVERSITY   (United States)

^c University of Minnesota   (United States)

Author keywords

Buffer insertion; Deep submicron; Interconnect synthesis; Layout; Physical design; Steiner tree

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; CONSTRAINT THEORY; ELECTRIC WIRE; GRAPH THEORY; INTERCONNECTION NETWORKS; OPTIMIZATION; RESOURCE ALLOCATION;

BUFFER INSERTION; DEEP SUBMICRON; INTERCONNECT SYNTHESIS; STEINER TREE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0037853079     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.810749     Document Type: Article

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