Buffered Steiner tree construction with wire sizing for interconnect layout optimization

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1996, Pages 44-49

  Okamoto, Takumi ^a   Cong, Jason ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; DYNAMIC PROGRAMMING; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; SEMICONDUCTOR DEVICE MODELS; TREES (MATHEMATICS);

BUFFERED STEINER TREE; REQUIRED ARRIVAL TIME; WIRE SIZING;

VLSI CIRCUITS;

EID: 0030410359     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)