Jitter-induced power/ground noise in CMOS PLLs: A design perspective

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2001, Pages 209-213

  Heydari, Payam ^a   Pedram, Massoud ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b University of Southern California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; JITTER; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE; STATISTICAL METHODS; VARIABLE FREQUENCY OSCILLATORS;

CLOCK GENERATORS; PHASE NOISE;

CMOS INTEGRATED CIRCUITS;

EID: 0035186884     PISSN: 10636404     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICCD.2001.955030     Document Type: Article

References (14)

1. Delta-I noise specification for a high performance computing machine
2. Simultaneous switching ground noise calculation for packaged CMOS devices
3. Di/dt noise in CMOS integrated circuits
4. Effects of simultaneous switching noise on the tapered buffer design
5. A general theory of phase noise in electrical oscillators
6. Oscillator jitter due to supply and substrate noise
7. Analysis of jitter due to power-supply noise in phase-locked loops
8. Noise properties of PLL systems
9. Analysis and optimization of ground bounce in digital CMOS circuits
10. A PLL clock generator with 5 to 110 MHz of lock range for microprocessors
11. A 2-1600MHz CMOS clock recovery PLL with low-vdd capability