Low-voltage and low-power logic, memory, and analog circuit techniques for SoCs using 90 nm technology and beyond

IEICE Transactions on Electronics

Volumn E89-C, Issue 3, 2006, Pages 250-262

  Ishibashi, Koichiro ^a,b,i   Fujimoto, Tetsuya ^a,c   Yamashita, Takahiro ^a,d   Okada, Hiroyuki ^a,e   Arima, Yukio ^a,f,j,k   Hashimoto, Yasuyuki ^a,g   Sakata, Kohji ^a,h   Minematsu, Isao ^a,b,i   Itoh, Yasuo ^a,d,l   Toda, Haruki ^a,d   Ichihashi, Motoi ^a,b   Komatsu, Yoshihide ^a,f,m   Hagiwara, Masato ^a,b   Tsukada, Toshiro ^a,n  

^a SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

^c SHARP CORPORATION   (Japan)

^d TOSHIBA CORPORATION   (Japan)

^e NEC CORPORATION   (Japan)

^f PANASONIC CORPORATION   (Japan)

^g ROHM CO LTD   (Japan)

^h SANYO ELECTRIC CO LTD   (Japan)

ⁱ IEEE

^j Matsushita   (Japan)

^k System LSI Technology Development Center   (Japan)

^l JAPAN SOCIETY OF APPLIED PHYSICS   (Japan)

^m NEC Corporation ^*

ⁿ TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

more..

Author keywords

90 nm; CMOS; Low power; Low voltage; SoC; Variability

Indexed keywords

ANALOG STORAGE; CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; ELECTRIC POTENTIAL; LEAKAGE CURRENTS; TRANSISTORS;

90 NM; LOW POWER; LOW VOLTAGE; SELF-ADJUSTED FORWARD BODY BIAS TECHNIQUES (SAFBB); SOC; VARIABILITY;

CIRCUIT THEORY;

EID: 33645765501     PISSN: 09168524     EISSN: 17451353     Source Type: Journal    
DOI: 10.1093/ietele/e89-c.3.250     Document Type: Article

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