Offset calibrating comparator array for 1.2-V, 6bit, 4-Gsample/s flash ADCs using 0.13μm generic CMOS technology

European Solid-State Circuits Conference

Volumn , Issue , 2003, Pages 711-714

  Okada, Hiroyuki ^a   Hashimoto, Yasuyuki ^a   Sakata, Kohji ^a   Tsukada, Toshiro ^a   Ishibashi, Koichiro ^a  

^a STARC   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; LOW SUPPLY VOLTAGES; OFFSET CALIBRATION; POWER SUPPLY;

CALIBRATION; CMOS INTEGRATED CIRCUITS; COMPARATORS (OPTICAL);

ANALOG TO DIGITAL CONVERSION;

EID: 4344690108     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2003.1257234     Document Type: Conference Paper

References (6)

1. P. Scholtens, and M. Vertregt, "A 6b 1. 6GsampIe/s Flash ADC in 0. 1 Sum CMOS using Averaging Termina-tion, " ISSCC Digest of Technical Papers, pp. 168-169, Feb. 2002.
2. M. Choi and A. A. Abidi, "A 6b 1. 3Gsample/s A/D Converter in 0. 35um CMOS, " ISSCC Digest of Technical Papers, pp. 126-127, Feb. 2001.
3. K. Uyttenhove and M. Steyaert, "A 1. 8-V, 6-bit, 1. 3 GHz Flash ADC in 0. 25um CMOS, " ESSCIRC Di-gest of Technical Papers, pp. 455-158, Sep. 2002.
4. K. Kattmann and J. Barrow, "A Technique for Reduc-ing Differential Non-Linearity Errors in Flash A/D Con-verters, " ISSCC digest of Technical Papers, pp. 170-171, Feb. 1991.
5. K. Bult and A. Buchwald, "An Embedded 240-mW 10-b 50-MS/s CMOS ADC in lW, " IEEE Journal of Solid-State Circuits, Vol. 32, No. 12, Dec. 1997.
6. J. Lin, and B. Haroun, "An Embedded 0. 8V/480uW 6b/"22MHz Flash ADC in 0. 13um Digital CMOS Process using Nonlinear Double-interpolation Technique, " ISSCC Digest of Technical Papers, pp. 308-309, Feb.