0.5 V 200 MHz 1-stage 32 b ALU using a body bias controlled SOI pass-gate logic

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 40, Issue , 1997, Pages 286-287

  Fuse, Tsuneaki ^a   Oowaki, Yukihito ^a   Yamada, Takashi ^a   Kamoshida, Masahiro ^a   Ohta, Masako ^a   Shino, Tomoaki ^a   Kawanaka, Shigeru ^a   Terauchi, Mamoru ^a   Yoshida, Takeshi ^a   Matsubara, Genso ^a   Yoshioka, Shinichi ^a   Watanabe, Shigeyoshi ^a   Yoshimi, Makoto ^a   Ohuchi, Kazunori ^a   Manabe, Sohei ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC LOADS; FLIP FLOP CIRCUITS; LEAKAGE CURRENTS; LOGIC DESIGN; LOGIC GATES; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD ELEMENTS; THRESHOLD LOGIC; VOLTAGE CONTROL;

ARITHMETIC LOGIC UNIT (ALU); BODY BIAS CONTROLLED SILICON ON INSULATOR (SOI) PASS GATE LOGIC; THRESHOLD VOLTAGE;

LOGIC CIRCUITS;

EID: 0031073501     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)