A V-driver circuit for lowering power of sub-0.1μm bus

2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Volumn , Issue , 2002, Pages 267-270

  Yamashita, T ^a   Arima, Y ^a   Ishibashi, K ^a  

^a SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUS DRIVERS; CMOS INTEGRATED CIRCUITS;

65 NM CMOS TECHNOLOGIES; DRIVER CIRCUIT; POWER REDUCTIONS; SIGNAL TRANSITION; SIMULATED RESULTS; TEST CHIPS;

RECONFIGURABLE HARDWARE;

EID: 84966335597     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APASIC.2002.1031583     Document Type: Conference Paper

References (7)

1. Y.Sasaki et al., "Multi-Aggressor relative window method for timing analysis including crosstalk delay degradation," CICC 2000, pp.495-498
2. Y.Shin et al., "Estimation of power distribution in VLSI interconnects," ISLPED 2001, pp.370-375
3. P.P.Sotiriadis et al., "Analysis and implementation of charge recycling for deep sub-micron buses," ISLPED 2001, pp.364-369
4. K.W.Kim et al., "Coupling delay optimization by temporal decorrelation using dual threshold voltage technique," DAC 2001, pp.732-737
5. K.Hirose et al.,., "A bus delay reduction technique considering crosstalk," DATE 2000, pp441-445
6. A.B.Kahng et al., "Interconnect tuning strategies for high-performance ICs," DATE 1998, pp.42.2-478
7. http://www.semichips.org/downloads/itrs-slides.pdf