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Volumn E83-C, Issue 11, 2000, Pages 1724-1732

Low-power area-efficient design of embedded high-speed A/D converters

Author keywords

Analog design method; High speed A D converter; Low power design

Indexed keywords


EID: 0013396689     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (5)

References (17)
  • 6
    • 0027576932 scopus 로고
    • An 8 bit 85-MS/s parallel pipeline A/D converter in 1 μm CMOS
    • April
    • C.S.G. Conriy, D.W. Cline, and P.R. Gray, "An 8 bit 85-MS/s parallel pipeline A/D converter in 1 μm CMOS," IEEE J. Solid-State Circuits, vol.28, no.4, pp.447-454, April 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.28 , Issue.4 , pp. 447-454
    • Conriy, C.S.G.1    Cline, D.W.2    Gray, P.R.3
  • 8
    • 0029269932 scopus 로고
    • A 10 b, 20 Msample/s, 35 mW pipeline A/D converter
    • March
    • T.B. Cho and P.R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE J. Solid-State Circuits, vol.30, no.3, pp.166-172, March 1995.
    • (1995) IEEE J. Solid-State Circuits , vol.30 , Issue.3 , pp. 166-172
    • Cho, T.B.1    Gray, P.R.2
  • 10
    • 0027853599 scopus 로고
    • A 15 b 1-Msamples/s digitally self-calibrated pipeline ADC
    • Dec.
    • A.N. Karanicolas, H.S. Lee, and K.L. Bacrania, "A 15 b 1-Msamples/s digitally self-calibrated pipeline ADC," IEEE J. Solid-State Circuits, vol.28, no.12, pp.1207-1215, Dec. 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.28 , Issue.12 , pp. 1207-1215
    • Karanicolas, A.N.1    Lee, H.S.2    Bacrania, K.L.3
  • 11
    • 0028417146 scopus 로고
    • A 12-b ks/s digitally self-calibrated pipelined algorithmic ADC
    • April
    • H.-S. Lee, "A 12-b ks/s digitally self-calibrated pipelined algorithmic ADC," IEEE J. Solid-State Circuits, vol.29, no.4, pp.509-515, April 1994.
    • (1994) IEEE J. Solid-State Circuits , vol.29 , Issue.4 , pp. 509-515
    • Lee, H.-S.1
  • 12
    • 0032680926 scopus 로고    scopus 로고
    • Low-power area efficient pipelined A/D converter design using single-ended amplifier
    • Feb.
    • D. Miyazaki, S. Kawahito, and Y. Tadokoro, "Low-power area efficient pipelined A/D converter design using single-ended amplifier," IEICE Trans. Fundamentals, vol.E82-A, no.2, pp.293-300, Feb. 1999.
    • (1999) IEICE Trans. Fundamentals , vol.E82-A , Issue.2 , pp. 293-300
    • Miyazaki, D.1    Kawahito, S.2    Tadokoro, Y.3
  • 14
    • 0030106088 scopus 로고    scopus 로고
    • A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS
    • March
    • D.W. Cline and P.R. Gray, "A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS," IEEE J. Solid-State Circuits, vol.31, no.3, pp.294-303, March 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , Issue.3 , pp. 294-303
    • Cline, D.W.1    Gray, P.R.2
  • 16
    • 0029267888 scopus 로고
    • An 85mW, 10 b, 40 Msamples/s CMOS parallel-pipelined ADC
    • March
    • K. Nakamura, M. Hotta, L.R. Carley, and D.J. Allstot, "An 85mW, 10 b, 40 Msamples/s CMOS parallel-pipelined ADC," IEEE J. Solid-State Circuits, vol.30, no.3, pp.173-183, March 1995.
    • (1995) IEEE J. Solid-State Circuits , vol.30 , Issue.3 , pp. 173-183
    • Nakamura, K.1    Hotta, M.2    Carley, L.R.3    Allstot, D.J.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.