A 16 mw 30 MSample/s 10 b pipelined A/D converter using a pseudo-differential architecture

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue SUPPL., 2002, Pages 134-135+437

  Miyazaki, Daisuke ^a   Furuta, Masanori ^a   Kawahito, Shoji ^a  

^a SHIZUOKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); BANDWIDTH; CAPACITORS; CMOS INTEGRATED CIRCUITS; ENERGY DISSIPATION;

PSEUDO-DIFFERENTIAL ARCHITECTURE;

ANALOG TO DIGITAL CONVERSION;

EID: 0036227049     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)