On designing via-configurable cell blocks for regular fabrics

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 198-203

  Ran, Yajun ^a   Marek Sadowska, Malgorzata ^a  

^a Santa Barbara   (United States)

Author keywords

Layout; Regular fabric; Via configurable

Indexed keywords

GATE ARRAYS; POWER CONSUMPTION; REGULAR FABRIC; VIA CONFIGURABLE;

ALGORITHMS; CMOS INTEGRATED CIRCUITS; ENERGY UTILIZATION; FLIP FLOP CIRCUITS; GATES (TRANSISTOR); TELECOMMUNICATION REPEATERS;

INTEGRATED CIRCUIT LAYOUT;

EID: 4444342520     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2004.240257     Document Type: Conference Paper

References (14)

1. A. V. Aho, J. E. Hopcroft, and J. D. Ullman. The Design and Analysis of Computer Algorithms. Addison-Wesley, 1974.
2. A. E. Caldwell, A. B. Kahng, and I. L. Markov. Can recursive bisection produce routable placements? In Proceedings of DAC, pages 260-263, 2000.
3. J. Cong and Y. Ding. FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. IEEE Trans. on CAD, 13(1):1-12, January 1994.
4. Y. B. Dhong and C. P. Tsang. High speed CMOS POS PLA using predischarged OR array and charge sharing AND array. IEEE Trans. on Circuits and Systems II, 39(8):557-564, August 1992.
5. S. P. Khatri et al. Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric. In Proceedings of ICCAD, pages 412-418, 2000.
6. Z. A. Lomnicki. Two-terminal series-parallel networks. Adv. in Appl. Prob., 4(1):109-150, April 1972.
7. R. L. Maziasz and J. P. Hayes. Layout Minimization of CMOS Cells. Kluwer Academic Publishers, 1992.
8. F. Mo and R. K. Brayton. River PLAs: A regular circuit structure. In Proceedings of DAC, pages 201-206, 2002.
9. F. Mo and R. K. Brayton. Whirlpool PLAs: A regular logic structure and their synthesis. In Proceedings of ICCAD, pages 543-550, 2002.
10. C. Patel, A. Cozzie, H. Schmit, and L. Pileggi. An architectural exploration of via patterned gate arrays. In Proceedings of ISPD, pages 184-189, 2003.
11. L. Pileggi et al. Exploring regular fabrics to optimize the performance-cost trade-off. In Proceedings of DAC, pages 782-787, 2003.
12. E. Sentovich et al. SIS: A system for sequential circuit analysis. Technical Report UCB/ERL M92/41, University of California, Berkeley, 1992.
13. T. Uehara and W. M. van Cleemput. Optimal layout of CMOS functional arrays. IEEE Trans. on Computers, 30(5):305-312, May 1981.
14. B. Zahiri. Structured ASICs: Opportunities and challenges. In Proceedings of ICCD, pages 404-409, 2003.