Synthesis and placement flow for gain-based programmable regular fabrics

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2003, Pages 197-203

  Hu, Bo ^a   Jiang, Hailin ^a   Liu, Qinghua ^a   Marek Sadowska, Malgorzata ^a  

^a University of California   (United States)

Author keywords

Gain; Programmable; Regular fabric

Indexed keywords

ALGORITHMS; ARRAYS; BOOLEAN FUNCTIONS; COMPUTER AIDED LOGIC DESIGN;

GAIN-BASED LOGIC BLOCKS (GLB);

VLSI CIRCUITS;

EID: 0037702459     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/640000.640041     Document Type: Conference Paper

References (13)

1. R. Bryant, K-T. Cheng, A. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J. Rabaey, A. Sangiovanni-Vincentelli, "Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI", Proc. IEEE, vol. 89, issue 3, Mar 2001, pp. 341-365.
2. V. Betz, J. Rose "VPR: A New Packing, Placement and Routing tool for FPGA research", Proc. Seventh FPLA, pp. 213-222, 1997.
3. J. Cong, Y. Ding, "FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs", IEEE trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 13 Issue 1, Jan 1994, pp. 1-12.
4. H. Dao, V.G. Oklobdzija, "Application of Logical Effort Techniques for Speed Optimization and Analysis of Representative Adders", Conference Record of the Thirty-Fifth Asilomar Conference on Signals, Systems and Computers, vol 2, 2001, pp: 1666-1669.
5. J. Grodstein, E. Lehman, H. Harkness, B. Grundmann, Y. Watanabe, "A Delay Model for Logic Synthesis of Continuously-Sized Networks", in Proc. ICCAD, pp. 458-462, 1995.
6. B. Hu, M. Marek-Sadowska, "Fine-granularity clustering for large-scale placement problems", Intl. Symp. on Physical Design, Apr 2003.
7. C.C. Lin, M. Marek-Sadowska, D. Gatlin, "On designing universal logic blocks and their application to FPGA design", IEEE trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 16, issue 5, May 1997, pp. 519-527.
8. W. Maly, "IC Design in High-Cost Nanometer-Technologies Era", Proc. DAC 2001, June 10-22, 2001, pp. 9-14.
9. F. Mo, R.K. Brayton, "Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design", Intl. Workshop on Logic and Synthesis, Jun 2002.
10. F. Mo, R.K. Brayton, "Whirlpool PLAs: a Regular Logic Structure and Their Synthesis", Intl. Conf. Computer-Aided Design, Nov. 2002.
11. E. Sentovich, K. Singh, C. Moon, H. Savoj, R. Brayton, and A. Sangiovanni-Vincentelli, "Sequential circuit design using synthesis and optimization", in IEEE Int. Conf. Comput. Design, 1992.
12. I. Sutherland, R. Sproull, "The theory of logical effort: designing for speed on the back of an envelope", Advanced Research in VLSI, 1991.
13. X.Y. Yu, V.G. Oklobdzija, W.W. Walker, "Application of Logical Effort on Design of Arithmetic Blocks", Conference Record of the Thirty-Fifth Asilomar Conference on Signals, Systems and Computers, vol 1, 2001, pp: 872-874.