On designing universal logic blocks and their application to FPGA design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 5, 1997, Pages 519-527

  Lin, Chih Chang ^a   Marek Sadowska, Malgorzata ^a   Fellow, ^a,b   Gatlin, Duane ^b  

^a MENTOR GRAPHICS CORPORATION   (United States)

^b University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED LOGIC DESIGN; COMPUTER ARCHITECTURE; FUNCTIONS; PARALLEL PROCESSING SYSTEMS; TABLE LOOKUP;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

LOGIC GATES;

EID: 0031147546     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.631214     Document Type: Article

References (24)

1. The Programmable Logic Data Book, Xilinx, San Jose, CA, 1993.
2. FPGA Data Book and Design Guide, Actel, Sunnyvale, CA, 1994.
3. K. S. Brace, R. L. Rudell, and R. E. Bryant, "Efficient implementation of a BDD package," in Proc. ACM/IEEE Design Automation Conf., 1990, pp. 40-45.
4. S. Brown, R. Francis, J. Rose, and Z. Vranesic, Field-Programmable Gate Arrays. Boston: Kluwer Academic, 1992.
5. R. E. Bryant, "Graph-based algorithms for Boolean function manipulation," IEEE Trans. Comput., vol. C35, pp. 667-691, 1986.
6. Y.-W. Chang and D. F. Wong, "Universal switch-module design for symmetric-array-based FPGA's," in Proc. ACM/SIGDA Int. Symp. FPGAs, 1996, pp. 80-86.
7. X. Chen and X. Wu, "The derivation of universal logic modules for n > 3 by algebraic means," in Proc. Inst. Elect. Eng., vol. 128, pt. E, pp. 205-211, 1981.
8. O. Coudert and J. C. Madre, "A unified framework for the formal verification of sequential circuits," in Proc. IEEE Int. Conf. ComputerAided Design, 1990, pp. 126-129.
9. C. R. Edwards, "A special class of universal logic gates (ULG) and their evaluation under the Walsh transform," Int. J. Electron., vol. 44, pp. 49-59, 1978.
10. A. E. Gamal, J. Greene, G. Reyneri, E. Rogoyski, K. A. El-Ayat, and A. Mohsen, "An architecture for electrically configurable gate arrays," IEEE J. Solid-State Circuits, vol. 24, pp. 394-398, 1989.
11. M. A. Harrison, Introduction to Switching and Automata Theory. New York: McGraw-Hill, 1965.
12. A. Jain and R. E. Bryant, "Inverter minimization in logic networks," presented at the IEEE Int. Workshop Logic Synthesis, 1993.
13. K. Karplus, "Using if-then-else DAG's to do technology mapping for field-programmable gate arrays," Rep. UCSC-CRL90-43, Univ. California, Santa Cruz, 1990.
14. K. Karplus, "Amap: A technology mapper for selector-based field-programmable gate arrays," in Proc. ACM/IEEE Design Automation Conf., 1991, pp. 244-247.
15. C.-C. Lin, M. Marek-Sadowska, and D. Gatlin, "Universal logic for FPGA design," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1994, pp. 164-168.
16. D. Long, "BDD-A binary decision diagram package," Tech. Rep., Carnegie-Mellon Univ., Pittsburgh, PA, 1993.
17. R. Murgai, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "An improved synthesis algorithm for multiplexor-based PGA's," in Proc. ACM/IEEE Design Automation Conf., 1992, pp. 380-386.
18. E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Sequential circuit design using synthesis and optimization," in Proc. IEEE Int. Conf. Comput. Design, 1992, pp. 328-333.
19. H. S. Stone, "Universal logic modules," in Recent Developments in Switching Theory, A. Mukhopadhyay, Ed. New York: Academic, 1971, ch. VI, pp. 229-254.
20. S. Thakur and D. F. Wong, "On designing ULM-based FPGA logic modules," in Proc. ACM/SIGDA Int. Symp. FPGAs, 1995, pp. 3-9.
21. H. J. Touati, H. Savoj, and B. Lin, "Implicit state enumeration of finite state machines using BDD's," in Proc. IEEE Int. Conf. Computer-Aided Design, 1990, pp. 130-133.
22. L. Trevillyan, "An experiment in technology mapping for FPGA's using a fixed library," presented at the IEEE Int. Workshop on Logic Synthesis, 1993.
23. Y.-L. Wu and D. Chang, "On the NP-completeness of regular 2-D FPGA routing architectures," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1994, pp. 362-366.
24. Z. Zilic and Z. G. Vranesic, "Using BDD's to design ULM's for FPGA's," in Proc. ACM/SIGDA Int. Symp. FPGAs, 1996, pp. 24-30.