The magic of a via-configurable regular fabric

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2004, Pages 338-343

  Ran, Yajun ^a   Marek Sadowska, Malgorzata ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; COMBINATORIAL CIRCUITS; COMPUTER PROGRAMMING; FEEDBACK; FORMAL LOGIC; GATEWAYS (COMPUTER NETWORKS); GENERAL PURPOSE COMPUTERS; RESOURCE ALLOCATION; SEQUENTIAL CIRCUITS; STATIC RANDOM ACCESS STORAGE;

AREA UTILIZATION; POWER CONSUMPTION; TRANSISTOR UTILIZATION; VIA-CONFIGURABLE GATE ARRAY (VCGA);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 17644403744     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. B. Hu, H. Jiang, Q. Liu, and M. Marek-Sadowska. Synthesis and placement flow for gain-based programmable regular fabrics. In Proceedings of International Symposium on Physical Design, pages 197-203, 2003.
2. C. Patel, A. Cozzie, H. Schmit, and L. Pileggi. An architectural exploration of via patterned gate arrays. In Proceedings of International Symposium on Physical Design, pages 184-189, 2003.
3. L. Pileggi et al. Exploring regular fabrics to optimize the performance-cost trade-off. In Proceedings of Design Automation Conference, pages 782-787, 2003.
4. Y. Ran and M. Marek-Sadowska. On designing viaconfigurable cell blocks for regular fabrics. In Proceedings of Design Automation Conference, pages 198-203, 2004.
5. N. H. E. Weste and K. Eshraghian. Principles of CMOS VLSI Design. Addison-Wesley, 1993.