The floating-point unit of the PowerPC 603e microprocessor

IBM Journal of Research and Development

Volumn 40, Issue 5, 1996, Pages 559-566

  Jessani, R M ^a,b,c,d,e   Olson, C H ^f,g  

^a MOTOROLA INC   (United States)

^b NATIONAL INSTITUTE OF TECHNOLOGY   (India)

^c UNIVERSITY OF TEXAS AT DALLAS   (United States)

^d ADVANCED MICRO DEVICES   (United States)

^e IEEE

^f IBM   (United States)

^g UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC;

PEAK CLOCK FREQUENCY; POWERPC 603E MICROPROCESSOR; SINGLE CHIP SUPERSCALAR MICROPROCESSOR;

MICROPROCESSOR CHIPS;

EID: 0030231341     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.405.0559     Document Type: Article

References (6)

1. E. Hokenck, R. K. Montoye, and F. W. Cook. "Second-Generation RISC Floating Point with Multiply-Add Fused," IEEE J. Solid-State Circuits 25, No. 5, 1207-1213 (October 1990).
2. R. K. Montoye, E. Hokenek, and S. L. Runyon, "Design of the IBM RISC System/6000 Floating-Point Execution Unit," IBM J. Res. Develop. 34, No. 1, 59-70 (January 1990).
3. T. Olson and B. Stewart, "Floating-Point Architecture of the AM29050," WESCON/90 Conference Record, November 13-15, 1990, pp. 214-217.
4. ANSI/IEEE Standard 754-1985 for Binary Floating-Point Arithmetic, American National Standards Institute, Washington, DC, 1988.
5. A. D. Booth, "A Signed Binary Multiplication Technique," Quart. J. Mech. Appl. Math. 4, Part 2, 236-KOA (1951).
6. C. S. Wallace, "A Suggestion for Fast Multipliers." IEEE Trans. Electron. Comput. EC-13, 14-17 (February 1964).