Modeling of nonvolatile floating gate quantum dot memory

Solid-State Electronics

Volumn 48, Issue 10-11 SPEC. ISS., 2004, Pages 2055-2059

  Hasaneen, El Sayed ^a   Heller, E ^b   Bansal, R ^a   Huang, W ^c   Jain, F ^a  

^a UNIVERSITY OF CONNECTICUT   (United States)

^b RSoft Design Group Inc   (United States)

^c UNITED STATES MILITARY ACADEMY   (United States)

Author keywords

Capacitance voltage; Charging operation; MOS resistance; Nonvolatile memory; Quantum dot; Tunneling

Indexed keywords

DIELECTRIC DEVICES; ELECTRIC CHARGE; ELECTRON TUNNELING; GATES (TRANSISTOR); HAMILTONIANS; MATHEMATICAL MODELS; MOSFET DEVICES; NUMERICAL ANALYSIS; POISSON DISTRIBUTION; PROBABILITY; SEMICONDUCTOR QUANTUM WELLS; THRESHOLD VOLTAGE;

CAPACITANCE-VOLTAGE; CHARGING OPERATION; METAL OXIDE SEMICONDUCTOR (MOS) RESISTANCE; NONVOLATILE MEMORY;

SEMICONDUCTOR QUANTUM DOTS;

EID: 3142700897     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2004.05.073     Document Type: Conference Paper

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