Code generation for functional validation of pipelined microprocessors

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 20, Issue 3, 2004, Pages 269-278

  Corno, Fulvio ^a   Sanchez, Ernesto ^a   Reorda, Matteo Sonza ^a   Squillero, Giovanni ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

Automatic test program generation; Evolutionary algorithms; Functional validation; Pipelined micro processors

Indexed keywords

COMPUTER SIMULATION; COMPUTER SOFTWARE; EVOLUTIONARY ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS; FORMAL LOGIC; PIPELINE PROCESSING SYSTEMS;

AUTOMATIC TEST PROGRAM GENERATION; FUNCTIONAL VALIDATION; PIPELINED MICROPROCESSORS;

MICROPROCESSOR CHIPS;

EID: 3042842163     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/B:JETT.0000029460.80721.4d     Document Type: Conference Paper

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