Superscalar processor validation at the microarchitecture level

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1999, Pages 300-305

  Utamaphethai, Noppanunt ^a   Blanton, R D ^a   Shen, John Paul ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; FINITE AUTOMATA; FORMAL LOGIC; MATHEMATICAL MODELS; SEQUENTIAL CIRCUITS;

AUTOMATIC TEST PATTERN GENERATION (ATPG); FINITE STATE MACHINE (FSM) TESTING;

MICROPROCESSOR CHIPS;

EID: 0032715240     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icvd.1999.745164     Document Type: Conference Paper

References (14)